6eaf8b3d89
Updated the devicetree source files to make use of the following upstreamed drivers: - xrx200 ethernet phy - reset controller unit - dwc2 - fpi Use our custom xrx200 ethernet phy compatible to support boards, which have switched the vr9 revision during lifetime, with a single devicetree source file. By switching to the dwc2 driver + usb phy framework, we don't need to used our custom gpio power patch and can use a fixed regulator instead. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Mathias Kresin <dev@kresin.me>
296 lines
5.4 KiB
Text
296 lines
5.4 KiB
Text
/dts-v1/;
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#include "vr9.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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/ {
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compatible = "avm,fritz3370", "lantiq,xway", "lantiq,vr9";
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model = "Fritz!Box WLAN 3370";
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chosen {
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bootargs = "console=ttyLTQ0,115200 ubi.mtd=1,512 root=/dev/mtdblock9";
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};
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aliases {
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led-boot = &power_green;
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led-failsafe = &power_red;
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led-running = &power_green;
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led-dsl = &dsl;
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led-internet = &info_green;
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led-wifi = &wifi;
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};
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memory@0 {
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reg = <0x0 0x8000000>;
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <100>;
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power {
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label = "power";
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gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_POWER>;
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};
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/* wifi {
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label = "wifi";
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gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
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linux,code = <BTN_1>;
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};*/
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};
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gpio-leds {
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compatible = "gpio-leds";
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power_green: power {
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label = "fritz3370:green:power";
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gpios = <&gpio 32 GPIO_ACTIVE_LOW>;
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default-state = "keep";
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};
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power_red: power2 {
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label = "fritz3370:red:power";
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gpios = <&gpio 33 GPIO_ACTIVE_LOW>;
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};
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info_red {
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label = "fritz3370:red:info";
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gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
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};
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wifi: wifi {
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label = "fritz3370:green:wlan";
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gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
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};
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dsl: dsl {
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label = "fritz3370:green:dsl";
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gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
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};
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lan {
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label = "fritz3370:green:lan";
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gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
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};
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info_green: info_green {
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label = "fritz3370:green:info";
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gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
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};
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};
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};
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ð0 {
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lan: interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mtd-mac-address = <&urlader 0x987>;
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mtd-mac-address-increment = <(-2)>;
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lantiq,switch;
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ethernet@0 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
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};
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ethernet@1 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <1>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
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};
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "gmii";
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phy-handle = <&phy11>;
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};
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ethernet@3 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phy-mode = "gmii";
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phy-handle = <&phy13>;
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};
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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reg = <0>;
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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&gphy0 {
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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&gphy1 {
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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&gpio {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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mdio {
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lantiq,groups = "mdio";
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lantiq,function = "mdio";
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};
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nand {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd", "nand cs1", "nand rdy";
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lantiq,function = "ebu";
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lantiq,pull = <1>;
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};
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phy-rst {
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lantiq,pins = "io37", "io44";
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lantiq,pull = <0>;
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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pcie-rst {
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lantiq,pins = "io38";
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lantiq,pull = <0>;
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lantiq,output = <1>;
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};
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};
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pins_spi_default: pins_spi_default {
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spi_in {
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lantiq,groups = "spi_di";
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lantiq,function = "spi";
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};
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spi_out {
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lantiq,groups = "spi_do", "spi_clk",
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"spi_cs4";
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lantiq,function = "spi";
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lantiq,output = <1>;
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};
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};
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};
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&localbus {
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nand@1 {
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compatible = "lantiq,nand-xway";
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bank-width = <2>;
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reg = <1 0x0 0x2000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x400000>;
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};
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partition@400000 {
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label = "rootfs_ubi";
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reg = <0x400000 0x3000000>;
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};
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partition@3400000 {
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label = "vr9_firmware";
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reg = <0x3400000 0x400000>;
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};
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partition@3800000 {
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label = "reserved";
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reg = <0x3800000 0x3000000>;
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};
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partition@6800000 {
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label = "config";
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reg = <0x6800000 0x200000>;
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};
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partition@6a00000 {
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label = "nand-filesystem";
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reg = <0x6a00000 0x1600000>;
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};
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};
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};
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};
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&pcie0 {
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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wifi@0,0 {
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compatible = "pci0,0";
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reg = <0 0 0 0 0>;
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qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
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};
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};
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};
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&spi {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pins_spi_default>;
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m25p80@4 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <4 0>;
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spi-max-frequency = <1000000>;
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urlader: partition@0 {
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reg = <0x0 0x20000>;
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label = "urlader";
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read-only;
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};
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partition@20000 {
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reg = <0x20000 0x10000>;
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label = "tffs (1)";
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read-only;
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};
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partition@30000 {
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reg = <0x30000 0x10000>;
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label = "tffs (2)";
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read-only;
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};
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};
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};
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/*
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* TODO: add phy-supply, gpio 5 GPIO_ACTIVE_HIGH and gpio 14 GPIO_ACTIVE_HIGH are
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* related
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*/
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&usb_phy0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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