011f2c26f1
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
220 lines
6.8 KiB
Diff
220 lines
6.8 KiB
Diff
From 057da8ee92db7c8caece571aa20f478f5cae1318 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 27 Sep 2016 09:03:13 -0700
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Subject: [PATCH] drm/vc4: Fix races when the CS reads from render targets.
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With the introduction of bin/render pipelining, the previous job may
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not be completed when we start binning the next one. If the previous
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job wrote our VBO, IB, or CS textures, then the binning stage might
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get stale or uninitialized results.
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Fixes the major rendering failure in glmark2 -b terrain.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and rendering jobs")
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Cc: stable@vger.kernel.org
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 19 ++++++++++++++++++-
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drivers/gpu/drm/vc4/vc4_gem.c | 13 +++++++++++++
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drivers/gpu/drm/vc4/vc4_render_cl.c | 21 +++++++++++++++++----
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drivers/gpu/drm/vc4/vc4_validate.c | 17 ++++++++++++++---
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4 files changed, 62 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -129,9 +129,16 @@ to_vc4_dev(struct drm_device *dev)
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struct vc4_bo {
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struct drm_gem_cma_object base;
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- /* seqno of the last job to render to this BO. */
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+ /* seqno of the last job to render using this BO. */
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uint64_t seqno;
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+ /* seqno of the last job to use the RCL to write to this BO.
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+ *
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+ * Note that this doesn't include binner overflow memory
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+ * writes.
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+ */
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+ uint64_t write_seqno;
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+
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/* List entry for the BO's position in either
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* vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
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*/
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@@ -227,6 +234,9 @@ struct vc4_exec_info {
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/* Sequence number for this bin/render job. */
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uint64_t seqno;
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+ /* Latest write_seqno of any BO that binning depends on. */
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+ uint64_t bin_dep_seqno;
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+
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/* Last current addresses the hardware was processing when the
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* hangcheck timer checked on us.
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*/
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@@ -241,6 +251,13 @@ struct vc4_exec_info {
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struct drm_gem_cma_object **bo;
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uint32_t bo_count;
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+ /* List of BOs that are being written by the RCL. Other than
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+ * the binner temporary storage, this is all the BOs written
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+ * by the job.
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+ */
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+ struct drm_gem_cma_object *rcl_write_bo[4];
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+ uint32_t rcl_write_bo_count;
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+
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/* Pointers for our position in vc4->job_list */
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struct list_head head;
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--- a/drivers/gpu/drm/vc4/vc4_gem.c
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+++ b/drivers/gpu/drm/vc4/vc4_gem.c
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@@ -483,6 +483,11 @@ vc4_update_bo_seqnos(struct vc4_exec_inf
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list_for_each_entry(bo, &exec->unref_list, unref_head) {
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bo->seqno = seqno;
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}
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+
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+ for (i = 0; i < exec->rcl_write_bo_count; i++) {
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+ bo = to_vc4_bo(&exec->rcl_write_bo[i]->base);
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+ bo->write_seqno = seqno;
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+ }
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}
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/* Queues a struct vc4_exec_info for execution. If no job is
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@@ -685,6 +690,14 @@ vc4_get_bcl(struct drm_device *dev, stru
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goto fail;
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ret = vc4_validate_shader_recs(dev, exec);
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+ if (ret)
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+ goto fail;
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+
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+ /* Block waiting on any previous rendering into the CS's VBO,
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+ * IB, or textures, so that pixels are actually written by the
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+ * time we try to read them.
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+ */
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+ ret = vc4_wait_for_seqno(dev, exec->bin_dep_seqno, ~0ull, true);
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fail:
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kfree(temp);
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--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
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+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
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@@ -45,6 +45,8 @@ struct vc4_rcl_setup {
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struct drm_gem_cma_object *rcl;
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u32 next_offset;
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+
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+ u32 next_write_bo_index;
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};
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static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
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@@ -407,6 +409,8 @@ static int vc4_rcl_msaa_surface_setup(st
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if (!*obj)
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return -EINVAL;
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+ exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
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+
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if (surf->offset & 0xf) {
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DRM_ERROR("MSAA write must be 16b aligned.\n");
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return -EINVAL;
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@@ -417,7 +421,8 @@ static int vc4_rcl_msaa_surface_setup(st
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static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
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struct drm_gem_cma_object **obj,
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- struct drm_vc4_submit_rcl_surface *surf)
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+ struct drm_vc4_submit_rcl_surface *surf,
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+ bool is_write)
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{
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uint8_t tiling = VC4_GET_FIELD(surf->bits,
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VC4_LOADSTORE_TILE_BUFFER_TILING);
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@@ -440,6 +445,9 @@ static int vc4_rcl_surface_setup(struct
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if (!*obj)
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return -EINVAL;
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+ if (is_write)
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+ exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
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+
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if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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if (surf == &exec->args->zs_write) {
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DRM_ERROR("general zs write may not be a full-res.\n");
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@@ -542,6 +550,8 @@ vc4_rcl_render_config_surface_setup(stru
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if (!*obj)
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return -EINVAL;
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+ exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
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+
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if (tiling > VC4_TILING_FORMAT_LT) {
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DRM_ERROR("Bad tiling format\n");
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return -EINVAL;
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@@ -599,15 +609,18 @@ int vc4_get_rcl(struct drm_device *dev,
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if (ret)
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return ret;
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- ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read);
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+ ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read,
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+ false);
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if (ret)
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return ret;
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- ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read);
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+ ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read,
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+ false);
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if (ret)
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return ret;
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- ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write);
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+ ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write,
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+ true);
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if (ret)
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return ret;
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--- a/drivers/gpu/drm/vc4/vc4_validate.c
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+++ b/drivers/gpu/drm/vc4/vc4_validate.c
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@@ -267,6 +267,9 @@ validate_indexed_prim_list(VALIDATE_ARGS
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if (!ib)
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return -EINVAL;
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+ exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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+ to_vc4_bo(&ib->base)->write_seqno);
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+
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if (offset > ib->base.size ||
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(ib->base.size - offset) / index_size < length) {
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DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n",
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@@ -555,8 +558,7 @@ static bool
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reloc_tex(struct vc4_exec_info *exec,
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void *uniform_data_u,
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struct vc4_texture_sample_info *sample,
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- uint32_t texture_handle_index)
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-
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+ uint32_t texture_handle_index, bool is_cs)
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{
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struct drm_gem_cma_object *tex;
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uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]);
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@@ -714,6 +716,11 @@ reloc_tex(struct vc4_exec_info *exec,
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*validated_p0 = tex->paddr + p0;
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+ if (is_cs) {
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+ exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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+ to_vc4_bo(&tex->base)->write_seqno);
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+ }
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+
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return true;
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fail:
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DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0);
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@@ -835,7 +842,8 @@ validate_gl_shader_rec(struct drm_device
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if (!reloc_tex(exec,
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uniform_data_u,
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&validated_shader->texture_samples[tex],
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- texture_handles_u[tex])) {
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+ texture_handles_u[tex],
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+ i == 2)) {
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return -EINVAL;
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}
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}
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@@ -867,6 +875,9 @@ validate_gl_shader_rec(struct drm_device
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uint32_t stride = *(uint8_t *)(pkt_u + o + 5);
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uint32_t max_index;
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+ exec->bin_dep_seqno = max(exec->bin_dep_seqno,
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+ to_vc4_bo(&vbo->base)->write_seqno);
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+
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if (state->addr & 0x8)
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stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff;
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