171 lines
6.4 KiB
Diff
171 lines
6.4 KiB
Diff
From adada33c4ee27efdec0b08e43768a68285a5710d Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Thu, 2 Jan 2014 19:49:56 +0100
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Subject: [PATCH 2/5] bgmac: initialize the DMA controller of core rev >= 4
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The DMA controller used in the device supported by GMAC with core rev
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>= 4 has some new options which are now set to the default values used
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in the Broadcom SDK.
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Subject: [PATCH 3/5] bgmac: add support for new BGMAC_CMDCFG_SR position on
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core rev >= 4
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The BGMAC_CMDCFG_SR register is at a different position on core rev >= 4
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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--- a/drivers/net/ethernet/broadcom/bgmac.c
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+++ b/drivers/net/ethernet/broadcom/bgmac.c
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@@ -97,6 +97,19 @@ static void bgmac_dma_tx_enable(struct b
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
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+ if (bgmac->core->id.rev >= 4) {
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+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
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+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
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+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
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+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
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+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
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+ }
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ctl |= BGMAC_DMA_TX_ENABLE;
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ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
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@@ -241,6 +254,16 @@ static void bgmac_dma_rx_enable(struct b
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
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+ if (bgmac->core->id.rev >= 4) {
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+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
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+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
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+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
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+
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+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
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+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
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+ }
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ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
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ctl |= BGMAC_DMA_RX_ENABLE;
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ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
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@@ -746,13 +769,13 @@ static void bgmac_cmdcfg_maskset(struct
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u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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u32 new_val = (cmdcfg & mask) | set;
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- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
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+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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if (new_val != cmdcfg || force)
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bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
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- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
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+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
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udelay(2);
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}
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@@ -977,7 +1000,7 @@ static void bgmac_chip_reset(struct bgma
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BGMAC_CMDCFG_PROM |
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BGMAC_CMDCFG_NLC |
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BGMAC_CMDCFG_CFE |
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- BGMAC_CMDCFG_SR,
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+ BGMAC_CMDCFG_SR(core->id.rev),
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false);
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bgmac->mac_speed = SPEED_UNKNOWN;
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bgmac->mac_duplex = DUPLEX_UNKNOWN;
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@@ -1020,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
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cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
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bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
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- BGMAC_CMDCFG_SR, true);
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+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
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udelay(2);
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cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
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bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
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--- a/drivers/net/ethernet/broadcom/bgmac.h
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+++ b/drivers/net/ethernet/broadcom/bgmac.h
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@@ -198,7 +198,9 @@
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#define BGMAC_CMDCFG_TAI 0x00000200
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#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
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#define BGMAC_CMDCFG_HD_SHIFT 10
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-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
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+#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
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+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
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+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
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#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
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#define BGMAC_CMDCFG_AE 0x00400000
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#define BGMAC_CMDCFG_CFE 0x00800000
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@@ -238,9 +240,34 @@
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#define BGMAC_DMA_TX_SUSPEND 0x00000002
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#define BGMAC_DMA_TX_LOOPBACK 0x00000004
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#define BGMAC_DMA_TX_FLUSH 0x00000010
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+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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+#define BGMAC_DMA_TX_MR_SHIFT 6
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+#define BGMAC_DMA_TX_MR_1 0
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+#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
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+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
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+#define BGMAC_DMA_TX_BL_SHIFT 18
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+#define BGMAC_DMA_TX_BL_16 0
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+#define BGMAC_DMA_TX_BL_32 1
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+#define BGMAC_DMA_TX_BL_64 2
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+#define BGMAC_DMA_TX_BL_128 3
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+#define BGMAC_DMA_TX_BL_256 4
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+#define BGMAC_DMA_TX_BL_512 5
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+#define BGMAC_DMA_TX_BL_1024 6
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+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
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+#define BGMAC_DMA_TX_PC_SHIFT 21
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+#define BGMAC_DMA_TX_PC_0 0
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+#define BGMAC_DMA_TX_PC_4 1
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+#define BGMAC_DMA_TX_PC_8 2
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+#define BGMAC_DMA_TX_PC_16 3
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+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
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+#define BGMAC_DMA_TX_PT_SHIFT 24
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+#define BGMAC_DMA_TX_PT_1 0
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+#define BGMAC_DMA_TX_PT_2 1
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+#define BGMAC_DMA_TX_PT_4 2
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+#define BGMAC_DMA_TX_PT_8 3
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#define BGMAC_DMA_TX_INDEX 0x04
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#define BGMAC_DMA_TX_RINGLO 0x08
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#define BGMAC_DMA_TX_RINGHI 0x0C
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@@ -268,8 +295,33 @@
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#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
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#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
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#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
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+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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+#define BGMAC_DMA_RX_MR_SHIFT 6
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+#define BGMAC_DMA_TX_MR_1 0
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+#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
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+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
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+#define BGMAC_DMA_RX_BL_SHIFT 18
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+#define BGMAC_DMA_RX_BL_16 0
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+#define BGMAC_DMA_RX_BL_32 1
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+#define BGMAC_DMA_RX_BL_64 2
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+#define BGMAC_DMA_RX_BL_128 3
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+#define BGMAC_DMA_RX_BL_256 4
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+#define BGMAC_DMA_RX_BL_512 5
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+#define BGMAC_DMA_RX_BL_1024 6
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+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
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+#define BGMAC_DMA_RX_PC_SHIFT 21
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+#define BGMAC_DMA_RX_PC_0 0
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+#define BGMAC_DMA_RX_PC_4 1
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+#define BGMAC_DMA_RX_PC_8 2
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+#define BGMAC_DMA_RX_PC_16 3
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+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
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+#define BGMAC_DMA_RX_PT_SHIFT 24
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+#define BGMAC_DMA_RX_PT_1 0
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+#define BGMAC_DMA_RX_PT_2 1
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+#define BGMAC_DMA_RX_PT_4 2
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+#define BGMAC_DMA_RX_PT_8 3
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#define BGMAC_DMA_RX_INDEX 0x24
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#define BGMAC_DMA_RX_RINGLO 0x28
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#define BGMAC_DMA_RX_RINGHI 0x2C
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