openwrtv3/target/linux/ramips/dts/DWR-116-A1.dts
Pawel Dembicki a5bd8de0bd ramips: add support for D-Link DWR-116-A1/2
The DWR-116-A1/2 Wireless Router is based on the MT7620N SoC.

Specification:

  MediaTek MT7620N (580 Mhz)
  32 MB of RAM
  8 MB of FLASH
  802.11bgn radio
  5x 10/100 Mbps Ethernet (1 WAN and 4 LAN)
  2x external, non-detachable antennas
  UART (J1 in A1, JP1 in A2) header on PCB (57600 8n1)
  6x LED (GPIO-controlled), 2x button
  JBOOT bootloader

Known issues:
WAN LED is drived by uartl tx pin. I decide to use this pin as
uartlite tx pin.

Installation:
Apply factory image via http web-gui.

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
2018-03-18 22:22:38 +01:00

104 lines
1.5 KiB
Text

/dts-v1/;
#include "mt7620n.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "dlink,dwr-116-a1", "ralink,mt7620n-soc";
model = "D-Link DWR-116 A1/A2";
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
wps {
label = "wps";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
gpio-leds {
compatible = "gpio-leds";
status {
label = "dwr-116-a1:green:status";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "dwr-116-a1:green:wifi";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partition@0 {
label = "jboot";
reg = <0x0 0x10000>;
read-only;
};
partition@10000 {
label = "firmware";
reg = <0x10000 0x7e0000>;
};
config: partition@7f0000 {
label = "config";
reg = <0x7f0000 0x10000>;
read-only;
};
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&pinctrl {
state_default: pinctrl0 {
default {
ralink,group = "i2c", "wled";
ralink,function = "gpio";
};
};
};
&ethernet {
mediatek,portmap = "llllw";
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
};