15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
From 4f217aaf4bca500f13b4c560a6bbb3708c8e5dc2 Mon Sep 17 00:00:00 2001
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From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Date: Fri, 1 Jul 2016 04:37:53 +0530
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Subject: [PATCH 69/93] armv8:pfe:frdm Reset external PHYs before driver
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starts
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- Disable CONFIG_RESET_PHY_R, it is resetting PHYs after driver started
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- Call reset_phy() before driver initialization
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Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Signed-off-by: Anji J <anji.jagarlmudi@freescale.com>
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---
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board/freescale/ls1012afrdm/eth.c | 1 +
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include/configs/ls1012afrdm.h | 1 -
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2 files changed, 1 insertion(+), 1 deletion(-)
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diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
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index 90ed66b..be17310 100644
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--- a/board/freescale/ls1012afrdm/eth.c
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+++ b/board/freescale/ls1012afrdm/eth.c
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@@ -46,6 +46,7 @@ int board_eth_init(bd_t *bis)
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struct mdio_info mac1_mdio_info;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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+ reset_phy();
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/*TODO Following config should be done for all boards, where is the right place to put this */
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out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
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diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
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index 432317d..3de0cea 100644
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--- a/include/configs/ls1012afrdm.h
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+++ b/include/configs/ls1012afrdm.h
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@@ -23,7 +23,6 @@
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#define EMAC2_PHY_ADDR 0x1
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_REALTEK
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-#define CONFIG_RESET_PHY_R
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#endif
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/*
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* USB
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--
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1.7.9.5
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