c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
From ee2a430c1691d0bac3098e8db3c29d8f023b04c2 Mon Sep 17 00:00:00 2001
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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Date: Fri, 29 Jan 2016 11:29:32 +0000
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Subject: [PATCH 55/70] PCI: designware: Remove PCI_PROBE_ONLY handling
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The PCIe designware host driver is not used in system configurations
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requiring the PCI_PROBE_ONLY flag to be set to prevent resources
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assignment, therefore the driver code handling the flag can be removed
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from the kernel.
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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Acked-by: Jingoo Han Jingoo Han <jingoohan1@gmail.com>
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Cc: Arnd Bergmann <arnd@arndb.de>
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Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
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Cc: Zhou Wang <wangzhou1@hisilicon.com>
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---
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drivers/pci/host/pcie-designware.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -556,13 +556,11 @@ int dw_pcie_host_init(struct pcie_port *
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pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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#endif
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- if (!pci_has_flag(PCI_PROBE_ONLY)) {
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- pci_bus_size_bridges(bus);
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- pci_bus_assign_resources(bus);
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+ pci_bus_size_bridges(bus);
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+ pci_bus_assign_resources(bus);
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- list_for_each_entry(child, &bus->children, node)
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- pcie_bus_configure_settings(child);
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- }
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+ list_for_each_entry(child, &bus->children, node)
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+ pcie_bus_configure_settings(child);
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pci_bus_add_devices(bus);
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return 0;
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