9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
95 lines
2.6 KiB
Diff
95 lines
2.6 KiB
Diff
From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Sun, 24 Jun 2018 09:39:41 +0200
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Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
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With the target now being fully OF based, we can drop the legacy clock
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registration code. All clocks are now probed via devicetree.
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 56 ------------------------------------------------
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arch/mips/ath79/common.h | 3 ---
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2 files changed, 59 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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}
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-void __init ath79_clocks_init(void)
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-{
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- const char *wdt;
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- const char *uart;
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-
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- if (soc_is_ar71xx())
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- ar71xx_clocks_init(ath79_pll_base);
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- else if (soc_is_ar724x() || soc_is_ar913x())
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- ar724x_clocks_init(ath79_pll_base);
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- else if (soc_is_ar933x())
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- ar933x_clocks_init(ath79_pll_base);
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- else if (soc_is_ar934x())
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- ar934x_clocks_init(ath79_pll_base);
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- else if (soc_is_qca953x())
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- qca953x_clocks_init(ath79_pll_base);
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- else if (soc_is_qca955x())
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- qca955x_clocks_init(ath79_pll_base);
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- else if (soc_is_qca956x() || soc_is_tp9343())
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- qca956x_clocks_init(ath79_pll_base);
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- else
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- BUG();
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-
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- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
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- wdt = "ahb";
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- uart = "ahb";
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- } else if (soc_is_ar933x()) {
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- wdt = "ahb";
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- uart = "ref";
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- } else {
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- wdt = "ref";
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- uart = "ref";
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- }
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-
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- clk_add_alias("wdt", NULL, wdt, NULL);
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- clk_add_alias("uart", NULL, uart, NULL);
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-}
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-
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-unsigned long __init
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-ath79_get_sys_clk_rate(const char *id)
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-{
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- struct clk *clk;
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- unsigned long rate;
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-
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- clk = clk_get(NULL, id);
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- if (IS_ERR(clk))
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- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
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-
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- rate = clk_get_rate(clk);
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- clk_put(clk);
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-
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- return rate;
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-}
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-
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-#ifdef CONFIG_OF
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static void __init ath79_clocks_init_dt(struct device_node *np)
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{
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struct clk *ref_clk;
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@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
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CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
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CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
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CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
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-
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-#endif
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--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -19,9 +19,6 @@
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#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
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#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
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-void ath79_clocks_init(void);
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-unsigned long ath79_get_sys_clk_rate(const char *id);
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-
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void ath79_ddr_ctrl_init(void);
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#endif /* __ATH79_COMMON_H */
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