022855baf2
This removes a lot of duplicate register and interrupt definitions by moving the xrx200-net definition to vr9.dtsi and making all devices re- use it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48547
316 lines
6.6 KiB
Text
316 lines
6.6 KiB
Text
/include/ "vr9.dtsi"
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/ {
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chosen {
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bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
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leds {
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boot = &power_green;
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failsafe = &power_red;
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running = &power_green;
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dsl = &dsl_green;
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internet = &internet_green;
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wifi = &wireless_green;
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};
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};
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memory@0 {
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reg = <0x0 0x8000000>;
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};
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fpi@10000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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ranges = <0x0 0x10000000 0xEEFFFFF>;
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reg = <0x10000000 0xEF00000>;
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
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1 0 0x4000000 0x4000010>; /* addsel1 */
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compatible = "lantiq,localbus", "simple-bus";
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};
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gpio: pinmux@E100B10 {
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compatible = "lantiq,pinctrl-xr9";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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interrupt-parent = <&icu0>;
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interrupts = <166 135 66 40 41 42 38>;
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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state_default: pinmux {
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exin3 {
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lantiq,groups = "exin3";
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lantiq,function = "exin";
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};
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mdio {
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lantiq,groups = "mdio";
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lantiq,function = "mdio";
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};
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gphy-leds {
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lantiq,groups = "gphy0 led1", "gphy1 led1",
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"gphy0 led2", "gphy1 led2";
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lantiq,function = "gphy";
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lantiq,pull = <2>;
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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stp {
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lantiq,groups = "stp";
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lantiq,function = "stp";
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lantiq,pull = <2>;
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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pci-in {
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lantiq,groups = "req1";
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lantiq,function = "pci";
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lantiq,output = <0>;
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lantiq,open-drain = <1>;
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lantiq,pull = <2>;
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};
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pci-out {
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lantiq,groups = "gnt1";
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lantiq,function = "pci";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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pci_rst {
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lantiq,pins = "io21";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <2>;
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};
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pcie-rst {
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lantiq,pins = "io38";
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lantiq,pull = <0>;
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lantiq,output = <1>;
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};
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ifxhcd-rst {
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lantiq,pins = "io33";
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lantiq,pull = <0>;
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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nand_out {
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lantiq,groups = "nand cle", "nand ale";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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nand_cs1 {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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};
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stp: stp@E100BB0 {
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compatible = "lantiq,gpio-stp-xway";
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reg = <0xE100BB0 0x40>;
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#gpio-cells = <2>;
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gpio-controller;
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lantiq,shadow = <0xffffff>;
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lantiq,groups = <0x7>;
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lantiq,dsl = <0x0>;
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lantiq,phy1 = <0x0>;
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lantiq,phy2 = <0x0>;
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};
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ifxhcd@E101000 {
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status = "okay";
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gpios = <&gpio 33 0>;
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lantiq,portmask = <0x3>;
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};
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ifxhcd@E106000 {
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status = "okay";
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gpios = <&gpio 33 0>;
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};
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pci@E105400 {
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status = "okay";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "lantiq,pci-xway";
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bus-range = <0x0 0x0>;
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ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
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0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
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reg = <0x7000000 0x8000 /* config space */
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0xE105400 0x400>; /* pci bridge */
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lantiq,bus-clock = <33333333>;
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/*lantiq,external-clock;*/
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lantiq,delay-hi = <0>; /* 0ns delay */
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lantiq,delay-lo = <0>; /* 0.0ns delay */
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30
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>;
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gpio-reset = <&gpio 21 0>;
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req-mask = <0x1>; /* GNT1 */
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};
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};
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gphy-xrx200 {
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compatible = "lantiq,phy-xrx200";
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firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/
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firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/
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phys = [ 00 01 ];
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <100>;
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reset {
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label = "reset";
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gpios = <&gpio 39 1>;
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linux,code = <0x198>;
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};
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rfkill {
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label = "rfkill";
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gpios = <&gpio 1 1>;
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linux,code = <0xf7>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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internet_red {
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label = "p2812hnufx:red:internet";
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gpios = <&stp 16 1>;
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};
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internet_green: internet_green {
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label = "p2812hnufx:green:internet";
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gpios = <&stp 17 1>;
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};
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dsl_green: dsl_green {
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label = "p2812hnufx:green:dsl";
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gpios = <&stp 18 1>;
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};
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dsl_orange {
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label = "p2812hnufx:orange:dsl";
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gpios = <&stp 19 1>;
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};
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wireless_orange {
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label = "p2812hnufx:orange:wlan";
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gpios = <&stp 20 1>;
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};
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wireless_green: wireless_green {
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label = "p2812hnufx:green:wlan";
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gpios = <&stp 21 1>;
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};
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power_red: power {
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label = "p2812hnufx:red:power";
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gpios = <&stp 22 1>;
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};
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power_green: power2 {
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label = "p2812hnufx:green:power";
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gpios = <&stp 23 1>;
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default-state = "keep";
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};
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phone1 {
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label = "p2812hnufx:green:phone";
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gpios = <&gpio 11 1>;
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};
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phone1warn {
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label = "p2812hnufx:orange:phone";
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gpios = <&gpio 12 1>;
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};
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phone2warn {
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label = "p2812hnufx:orange:phone2";
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gpios = <&gpio 26 1>;
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};
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phone2 {
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label = "p2812hnufx:green:phone2";
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gpios = <&gpio 28 1>;
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};
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};
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};
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ð0 {
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lan: interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mac-address = [ 00 11 22 33 44 55 ];
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lantiq,switch;
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ethernet@0 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <0>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet@1 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <1>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "gmii";
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phy-handle = <&phy11>;
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};
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ethernet@4 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phy-mode = "gmii";
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phy-handle = <&phy13>;
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};
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ethernet@5 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <5>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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