02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
From 9f6deb688f4cb733cd3f36e0cc88f14d2f81982d Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Mon, 10 Feb 2014 18:35:50 +0800
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Subject: [PATCH] ARM: dts: sun7i: Add pin muxing options for the GMAC
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The A20 has EMAC and GMAC muxed on the same pins.
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Add pin sets with gmac function for MII and RGMII mode to the DTSI.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -492,6 +492,32 @@
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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+
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+ gmac_pins_mii_a: gmac_mii@0 {
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+ allwinner,pins = "PA0", "PA1", "PA2",
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+ "PA3", "PA4", "PA5", "PA6",
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+ "PA7", "PA8", "PA9", "PA10",
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+ "PA11", "PA12", "PA13", "PA14",
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+ "PA15", "PA16";
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+ allwinner,function = "gmac";
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+ allwinner,drive = <0>;
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+ allwinner,pull = <0>;
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+ };
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+
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+ gmac_pins_rgmii_a: gmac_rgmii@0 {
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+ allwinner,pins = "PA0", "PA1", "PA2",
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+ "PA3", "PA4", "PA5", "PA6",
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+ "PA7", "PA8", "PA10",
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+ "PA11", "PA12", "PA13",
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+ "PA15", "PA16";
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+ allwinner,function = "gmac";
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+ /*
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+ * data lines in RGMII mode use DDR mode
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+ * and need a higher signal drive strength
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+ */
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+ allwinner,drive = <3>;
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+ allwinner,pull = <0>;
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+ };
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};
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timer@01c20c00 {
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