b0ae41f849
According to the vendor tarball, the TD-w8900GB's flash has 64k erase block size, but CFE spans two blocks. So fixup the image offset accordingly but keep block size at its default (64k). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> [jogo: add commit message, add image offset, change nvram offset] Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 43572
133 lines
2.7 KiB
Diff
133 lines
2.7 KiB
Diff
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -503,6 +503,112 @@ static struct board_info __initdata boar
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},
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};
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+static struct board_info __initdata board_gw6200 = {
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+ .name = "GW6200",
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+ .expected_cpu_id = 0x6348,
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+
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+ .has_uart0 = 1,
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+ .has_enet0 = 1,
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+ .has_enet1 = 1,
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+ .has_pci = 1,
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+
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+ .enet0 = {
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+ .has_phy = 1,
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+ .use_internal_phy = 1,
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+ },
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+ .enet1 = {
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+ .force_speed_100 = 1,
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+ .force_duplex_full = 1,
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+ },
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+
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+ .has_ohci0 = 1,
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+
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+ .has_dsp = 1,
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+ .dsp = {
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+ .gpio_rst = 8, /* FIXME: What is real GPIO here? */
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+ .gpio_int = 34,
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+ .ext_irq = 2,
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+ .cs = 2,
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+ },
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+
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+ .leds = {
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+ {
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+ .name = "GW6200:green:line1",
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+ .gpio = 4,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "GW6200:green:line2",
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+ .gpio = 5,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "GW6200:green:line3",
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+ .gpio = 6,
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+ .active_low = 1,
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+ },
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+ {
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+ .name = "GW6200:green:tel",
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+ .gpio = 7,
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+ .active_low = 1,
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+ },
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+ },
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+ .buttons = {
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+ {
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+ .desc = "reset",
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+ .gpio = 36,
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+ .active_low = 1,
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+ .type = EV_KEY,
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+ .code = KEY_RESTART,
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+ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL,
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+ },
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+ },
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+};
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+
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+static struct board_info __initdata board_gw6000 = {
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+ .name = "GW6000",
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+ .expected_cpu_id = 0x6348,
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+
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+ .has_uart0 = 1,
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+ .has_enet0 = 1,
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+ .has_enet1 = 1,
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+ .has_pci = 1,
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+
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+ .enet0 = {
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+ .has_phy = 1,
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+ .use_internal_phy = 1,
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+ },
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+ .enet1 = {
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+ .force_speed_100 = 1,
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+ .force_duplex_full = 1,
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+ },
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+
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+ .has_ohci0 = 1,
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+
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+ .has_dsp = 1,
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+ .dsp = {
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+ .gpio_rst = 6,
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+ .gpio_int = 34,
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+ .ext_irq = 2,
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+ .cs = 2,
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+ },
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+
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+ /* GW6000 has no GPIO-controlled leds */
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+
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+ .buttons = {
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+ {
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+ .desc = "reset",
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+ .gpio = 36,
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+ .active_low = 1,
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+ .type = EV_KEY,
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+ .code = KEY_RESTART,
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+ .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL,
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+ },
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+ },
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+};
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+
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+
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+
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static struct board_info __initdata board_FAST2404 = {
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.name = "F@ST2404",
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.expected_cpu_id = 0x6348,
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@@ -1303,6 +1409,8 @@ static const struct board_info __initcon
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#ifdef CONFIG_BCM63XX_CPU_6348
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&board_96348r,
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&board_96348gw,
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+ &board_gw6000,
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+ &board_gw6200,
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&board_96348gw_10,
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&board_96348gw_11,
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&board_FAST2404,
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@@ -1349,6 +1457,8 @@ static struct of_device_id const bcm963x
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{ .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, },
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{ .compatible = "sagem,f@st2404", .data = &board_FAST2404, },
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{ .compatible = "t-com,spw500v", .data = &board_spw500v, },
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+ { .compatible = "tecom,gw6000", .data = &board_gw6000, },
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+ { .compatible = "tecom,gw6200", .data = &board_gw6200, },
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{ .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, },
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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