c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
172 lines
4.7 KiB
Diff
172 lines
4.7 KiB
Diff
From 3677d22ed7e3a631f35e2addc4e2181f6215e4b0 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:29 -0300
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Subject: [PATCH 143/203] mtd: nand: pxa3xx: Add driver-specific ECC BCH
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support
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This commit adds the BCH ECC support available in NFCv2 controller.
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Depending on the detected required strength the respective ECC layout
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is selected.
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This commit adds an empty ECC layout, since support to access large
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pages is first required. Once that support is added, a proper ECC
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layout will be added as well.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 86 +++++++++++++++++++++++++++++++++---------
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1 file changed, 69 insertions(+), 17 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -58,6 +58,7 @@
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#define NDPCR (0x18) /* Page Count Register */
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#define NDBDR0 (0x1C) /* Bad Block Register 0 */
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#define NDBDR1 (0x20) /* Bad Block Register 1 */
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+#define NDECCCTRL (0x28) /* ECC control */
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#define NDDB (0x40) /* Data Buffer */
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#define NDCB0 (0x48) /* Command Buffer0 */
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#define NDCB1 (0x4C) /* Command Buffer1 */
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@@ -198,6 +199,7 @@ struct pxa3xx_nand_info {
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int cs;
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int use_ecc; /* use HW ECC ? */
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+ int ecc_bch; /* using BCH ECC? */
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int use_dma; /* use DMA ? */
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int use_spare; /* use spare ? */
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int need_wait;
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@@ -205,6 +207,8 @@ struct pxa3xx_nand_info {
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unsigned int fifo_size; /* max. data size in the FIFO */
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unsigned int data_size; /* data to be read from FIFO */
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unsigned int oob_size;
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+ unsigned int spare_size;
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+ unsigned int ecc_size;
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int retcode;
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/* cached register value */
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@@ -339,19 +343,12 @@ static void pxa3xx_set_datasize(struct p
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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info->data_size = info->fifo_size;
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- if (!oob_enable) {
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- info->oob_size = 0;
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+ if (!oob_enable)
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return;
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- }
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- switch (info->fifo_size) {
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- case 2048:
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- info->oob_size = (info->use_ecc) ? 40 : 64;
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- break;
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- case 512:
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- info->oob_size = (info->use_ecc) ? 8 : 16;
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- break;
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- }
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+ info->oob_size = info->spare_size;
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+ if (!info->use_ecc)
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+ info->oob_size += info->ecc_size;
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}
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/**
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@@ -366,10 +363,15 @@ static void pxa3xx_nand_start(struct pxa
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ndcr = info->reg_ndcr;
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- if (info->use_ecc)
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+ if (info->use_ecc) {
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ndcr |= NDCR_ECC_EN;
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- else
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+ if (info->ecc_bch)
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+ nand_writel(info, NDECCCTRL, 0x1);
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+ } else {
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ndcr &= ~NDCR_ECC_EN;
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+ if (info->ecc_bch)
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+ nand_writel(info, NDECCCTRL, 0x0);
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+ }
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if (info->use_dma)
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ndcr |= NDCR_DMA_EN;
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@@ -1071,6 +1073,41 @@ static int pxa3xx_nand_sensing(struct px
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return 0;
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}
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+static int pxa_ecc_init(struct pxa3xx_nand_info *info,
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+ struct nand_ecc_ctrl *ecc,
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+ int strength, int page_size)
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+{
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+ /*
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+ * We don't use strength here as the PXA variant
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+ * is used with non-ONFI compliant devices.
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+ */
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+ if (page_size == 2048) {
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+ info->spare_size = 40;
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+ info->ecc_size = 24;
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+ ecc->mode = NAND_ECC_HW;
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+ ecc->size = 512;
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+ ecc->strength = 1;
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+ return 1;
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+
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+ } else if (page_size == 512) {
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+ info->spare_size = 8;
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+ info->ecc_size = 8;
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+ ecc->mode = NAND_ECC_HW;
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+ ecc->size = 512;
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+ ecc->strength = 1;
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+ return 1;
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+ }
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+ return 0;
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+}
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+
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+static int armada370_ecc_init(struct pxa3xx_nand_info *info,
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+ struct nand_ecc_ctrl *ecc,
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+ int strength, int page_size)
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+{
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+ /* Unimplemented yet */
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+ return 0;
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+}
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+
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static int pxa3xx_nand_scan(struct mtd_info *mtd)
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{
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struct pxa3xx_nand_host *host = mtd->priv;
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@@ -1141,13 +1178,13 @@ static int pxa3xx_nand_scan(struct mtd_i
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pxa3xx_flash_ids[1].name = NULL;
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def = pxa3xx_flash_ids;
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KEEP_CONFIG:
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- chip->ecc.mode = NAND_ECC_HW;
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- chip->ecc.size = info->fifo_size;
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- chip->ecc.strength = 1;
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-
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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chip->options |= NAND_BUSWIDTH_16;
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+ /* Device detection must be done with ECC disabled */
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+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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+ nand_writel(info, NDECCCTRL, 0x0);
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+
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if (nand_scan_ident(mtd, 1, def))
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return -ENODEV;
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@@ -1162,6 +1199,21 @@ KEEP_CONFIG:
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chip->bbt_md = &bbt_mirror_descr;
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}
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+ if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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+ ret = armada370_ecc_init(info, &chip->ecc,
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+ chip->ecc_strength_ds,
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+ mtd->writesize);
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+ else
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+ ret = pxa_ecc_init(info, &chip->ecc,
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+ chip->ecc_strength_ds,
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+ mtd->writesize);
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+ if (!ret) {
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+ dev_err(&info->pdev->dev,
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+ "ECC strength %d at page size %d is not supported\n",
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+ chip->ecc_strength_ds, mtd->writesize);
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+ return -ENODEV;
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+ }
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+
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/* calculate addressing information */
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if (mtd->writesize >= 2048)
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host->col_addr_cycles = 2;
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