openwrtv3/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200.dtsi

#include "vr9.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>

/ {
	memory@0 {
		reg = <0x0 0x7f00000>;
	};

	usb_vbus: regulator-usb-vbus {
		compatible = "regulator-fixed";

		regulator-name = "USB_VBUS";

		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&eth0 {
	lan: interface@0 {
		compatible = "lantiq,xrx200-pdi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;
		mtd-mac-address = <&romfile 0xf100>;
		lantiq,switch;

		ethernet@0 {
			compatible = "lantiq,xrx200-pdi-port";
			reg = <0>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;
			// gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
		};
		ethernet@5 {
			compatible = "lantiq,xrx200-pdi-port";
			reg = <5>;
			phy-mode = "rgmii";
			phy-handle = <&phy5>;
		};
		ethernet@2 {
			compatible = "lantiq,xrx200-pdi-port";
			reg = <2>;
			phy-mode = "gmii";
			phy-handle = <&phy11>;
		};
		ethernet@3 {
			compatible = "lantiq,xrx200-pdi-port";
			reg = <4>;
			phy-mode = "gmii";
			phy-handle = <&phy13>;
		};
	};

	mdio@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "lantiq,xrx200-mdio";
		reg = <0>;

		phy0: ethernet-phy@0 {
			reg = <0x0>;
			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
		};
		phy5: ethernet-phy@5 {
			reg = <0x5>;
			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
		};
		phy11: ethernet-phy@11 {
			reg = <0x11>;
			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
		};
		phy13: ethernet-phy@13 {
			reg = <0x13>;
			compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
		};
	};
};

&gphy0 {
	lantiq,gphy-mode = <GPHY_MODE_GE>;
};

&gphy1 {
	lantiq,gphy-mode = <GPHY_MODE_GE>;
};

&gpio {
	pinctrl-names = "default";
	pinctrl-0 = <&state_default>;

	state_default: pinmux {
		mdio {
			lantiq,groups = "mdio";
			lantiq,function = "mdio";
		};
		gphy-leds {
			lantiq,groups = "gphy0 led1", "gphy1 led1";
			lantiq,function = "gphy";
			lantiq,pull = <2>;
			lantiq,open-drain = <0>;
			lantiq,output = <1>;
		};
		phy-rst {
			lantiq,pins = "io42";
			lantiq,pull = <0>;
			lantiq,open-drain = <0>;
			lantiq,output = <1>;
		};
		pcie-rst {
			lantiq,pins = "io38";
			lantiq,pull = <0>;
			lantiq,output = <1>;
		};
	};
	pins_spi_default: pins_spi_default {
		spi_in {
			lantiq,groups = "spi_di";
			lantiq,function = "spi";
		};
		spi_out {
			lantiq,groups = "spi_do", "spi_clk",
				"spi_cs4";
			lantiq,function = "spi";
			lantiq,output = <1>;
		};
	};
};

&pci0 {
	status = "okay";
	gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
};

&spi {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pins_spi_default>;

	m25p80@4 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <4 0>;
		spi-max-frequency = <33250000>;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				reg = <0x0 0x20000>;
				label = "u-boot";
				read-only;
			};

			partition@20000 {
				reg = <0x20000 0xf90000>;
				label = "firmware";
			};

			partition@fb0000 {
				reg = <0xfb0000 0x10000>;
				label = "radioDECT";
				read-only;
			};

			partition@fc0000 {
				reg = <0xfc0000 0x10000>;
				label = "config";
				read-only;
			};

			romfile: partition@fd0000 {
				reg = <0xfd0000 0x10000>;
				label = "romfile";
				read-only;
			};

			partition@fe0000 {
				reg = <0xfe0000 0x10000>;
				label = "rom";
				read-only;
			};

			partition@ff0000 {
				reg = <0xff0000 0x10000>;
				label = "radio";
				read-only;
			};
		};
	};
};

&usb_phy0 {
	status = "okay";
};

&usb_phy1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	vbus-supply = <&usb_vbus>;
};

&usb1 {
	status = "okay";
	vbus-supply = <&usb_vbus>;
};