f577cb25c0
The following patches were dropped because they are already applied upstream: - 0038-MIPS-lantiq-fpi-on-ar9.patch - 0039-MIPS-lantiq-initialize-usb-on-boot.patch - 0042-USB-DWC2-big-endian-support.patch - 0043-gpio-stp-xway-fix-phy-mask.patch All other patches were simply refreshed, except the following: - 0001-MIPS-lantiq-add-pcie-driver.patch Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled some PMU gates for the vrx200 / VR9 SoCs) were removed since the upstream kernel disables unused PMU gates automatically (since 95135bfa7ead1becc2879230f72583dde2b71a0c "MIPS: Lantiq: Deactivate most of the devices by default"). - 0025-NET-MIPS-lantiq-adds-xrx200-net.patch Since OpenWrt commit 55ba20afcc2fe785146316e5be2c2473cb329885 drivers should use of_get_mac_address(). of_get_mac_address_mtd is not available for drivers anymore since it's called automatically within of_get_mac_address(). - 0028-NET-lantiq-various-etop-fixes.patch Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch While refreshing the kernel configuration SPI support had to be moved to config-4.4 because otherwise M25P80 was disabled. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48307
28 lines
989 B
Diff
28 lines
989 B
Diff
From 57b588c950b7e04e0f22393ad439299ba4fda9c3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 26 Nov 2015 11:00:09 +0100
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Subject: [PATCH] pinctrl/lantiq: Fix GPIO Setup of GPIO Port3
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Some special handling of GPIO Port 3 is needed because of
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some hardware thingofabob.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Martin Schiller <mschiller@tdt.de>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-xway.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/pinctrl/pinctrl-xway.c
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+++ b/drivers/pinctrl/pinctrl-xway.c
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@@ -1570,6 +1570,10 @@ static int xway_gpio_dir_out(struct gpio
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{
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struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
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+ if (PORT(pin) == PORT3)
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+ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
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+ else
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+ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
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gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
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xway_gpio_set(chip, pin, val);
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