f3f3f52259
Combine two pcie patches (2nd patch undid the 1st patch) together and refresh the other affected patches Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 34132
128 lines
3.6 KiB
Diff
128 lines
3.6 KiB
Diff
--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,4 +1,4 @@
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-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
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+obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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obj-$(CONFIG_MACH_GW2388) += laguna.o
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -198,6 +198,10 @@ static void __init cns3420_init(void)
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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+ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
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+ NR_IRQS_CNS3XXX);
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+ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
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+ NR_IRQS_CNS3XXX + 32);
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pm_power_off = cns3xxx_power_off;
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}
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -21,7 +21,6 @@
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#include <asm/hardware/gic.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/cache-l2x0.h>
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-#include <asm/gpio.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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@@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
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},
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};
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-static inline void gpio_line_config(u8 line, u32 direction)
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-{
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- u32 reg;
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- if (direction) {
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- if (line < 32) {
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- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg |= (1 << line);
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- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- } else {
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- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg |= (1 << (line - 32));
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- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- }
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- } else {
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- if (line < 32) {
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- reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg &= ~(1 << line);
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- __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- } else {
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- reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- reg &= ~(1 << (line - 32));
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- __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
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- }
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- }
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-}
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-
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-static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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-{
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- gpio_line_config(gpio, CNS3XXX_GPIO_IN);
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- return 0;
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-}
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-
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-static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
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-{
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- gpio_line_set(gpio, level);
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- gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
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- return 0;
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-}
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-
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-static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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-{
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- return gpio_get_value(gpio);
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-}
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-
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-static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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-{
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- gpio_set_value(gpio, value);
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-}
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-
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-static struct gpio_chip cns3xxx_gpio_chip = {
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- .label = "CNS3XXX_GPIO_CHIP",
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- .direction_input = cns3xxx_gpio_direction_input,
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- .direction_output = cns3xxx_gpio_direction_output,
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- .get = cns3xxx_gpio_get_value,
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- .set = cns3xxx_gpio_set_value,
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- .base = 0,
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- .ngpio = 64,
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-};
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-
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void __init cns3xxx_common_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
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#endif
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iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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-
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- gpiochip_add(&cns3xxx_gpio_chip);
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}
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/* used by entry-macro.S */
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -366,7 +366,8 @@ config ARCH_CLPS711X
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config ARCH_CNS3XXX
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bool "Cavium Networks CNS3XXX family"
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select CPU_V6K
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- select ARCH_WANT_OPTIONAL_GPIOLIB
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+ select ARCH_REQUIRE_GPIOLIB
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+ select GENERIC_IRQ_CHIP
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select GENERIC_CLOCKEVENTS
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select ARM_GIC
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select CLKDEV_LOOKUP
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--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
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#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
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#undef NR_IRQS
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-#define NR_IRQS NR_IRQS_CNS3XXX
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+#define NR_IRQS (NR_IRQS_CNS3XXX + 64)
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#endif
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#endif /* __MACH_BOARD_CNS3XXX_H */
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