36d98e6c7a
The MT7620 uses a 2 bit wide configuration of the mdio. Signed-off-by: Michael Lee <igvtee@gmail.com>
42 lines
1.9 KiB
Diff
42 lines
1.9 KiB
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -114,9 +114,14 @@
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#define MT7620_GPIO_MODE_WDT_MASK 0x3
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#define MT7620_GPIO_MODE_WDT_SHIFT 21
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+#define MT7620_GPIO_MODE_MDIO 0
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+#define MT7620_GPIO_MODE_MDIO_REFCLK 1
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+#define MT7620_GPIO_MODE_MDIO_GPIO 2
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+#define MT7620_GPIO_MODE_MDIO_MASK 0x3
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+#define MT7620_GPIO_MODE_MDIO_SHIFT 7
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+
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#define MT7620_GPIO_MODE_I2C 0
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#define MT7620_GPIO_MODE_UART1 5
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-#define MT7620_GPIO_MODE_MDIO 8
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#define MT7620_GPIO_MODE_RGMII1 9
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#define MT7620_GPIO_MODE_RGMII2 10
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#define MT7620_GPIO_MODE_SPI 11
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -55,7 +55,10 @@ static int dram_type;
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static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
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static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
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static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
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-static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
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+static struct rt2880_pmx_func mdio_grp[] = {
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+ FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
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+ FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
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+};
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static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
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static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
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static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
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@@ -92,7 +95,8 @@ static struct rt2880_pmx_group mt7620a_p
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GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
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GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
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MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
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- GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
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+ GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
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+ MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
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GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
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GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
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GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
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