437 lines
12 KiB
Diff
437 lines
12 KiB
Diff
diff -Nur linux-2.6.17/arch/mips/aruba/irq.c linux-2.6.17-openwrt/arch/mips/aruba/irq.c
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--- linux-2.6.17/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.17-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
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@@ -0,0 +1,433 @@
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+/**************************************************************************
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+ *
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+ * BRIEF MODULE DESCRIPTION
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+ * Interrupt routines for IDT EB434 boards / Atheros boards
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+ * Modified by Aruba Networks
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+ *
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+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ *
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+ **************************************************************************
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+ * May 2004 rkt, neb
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+ *
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+ * Initial Release
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+ *
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+ *
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+ *
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+ **************************************************************************
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+ */
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+
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/kernel_stat.h>
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+#include <linux/module.h>
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+#include <linux/signal.h>
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+#include <linux/sched.h>
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+#include <linux/types.h>
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+#include <linux/interrupt.h>
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+#include <linux/ioport.h>
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+#include <linux/timex.h>
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+#include <linux/slab.h>
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+#include <linux/random.h>
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+#include <linux/delay.h>
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+
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+#include <asm/bitops.h>
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+#include <asm/bootinfo.h>
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+#include <asm/io.h>
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+#include <asm/mipsregs.h>
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+#include <asm/system.h>
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+#include <asm/idt-boards/rc32434/rc32434.h>
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+#include <asm/idt-boards/rc32434/rc32434_gpio.h>
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+
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+#include <asm/irq.h>
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+
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+#undef DEBUG_IRQ
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+#ifdef DEBUG_IRQ
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+/* note: prints function name for you */
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+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
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+#else
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+#define DPRINTK(fmt, args...)
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+#endif
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+
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+extern void aruba_timer_interrupt(struct pt_regs *regs);
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+static unsigned int startup_irq(unsigned int irq);
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+static void end_irq(unsigned int irq_nr);
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+static void mask_and_ack_irq(unsigned int irq_nr);
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+static void aruba_enable_irq(unsigned int irq_nr);
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+static void aruba_disable_irq(unsigned int irq_nr);
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+
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+extern void __init init_generic_irq(void);
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+
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+typedef struct {
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+ u32 mask;
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+ volatile u32 *base_addr;
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+} intr_group_t;
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+
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+static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
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+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
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+};
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+
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+#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
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+#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003014)))
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+#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)(0xbc003014))) = (val), READ_MASK_MERLOT())
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+
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+static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
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+ {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
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+ {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
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+ {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
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+ {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
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+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
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+};
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+
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+#define READ_PEND_MUSCAT(base) (*(base))
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+#define READ_MASK_MUSCAT(base) (*(base + 2))
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+#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
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+
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+static inline int irq_to_group(unsigned int irq_nr)
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+{
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ return 0;
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+ }
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+}
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+
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+static inline int group_to_ip(unsigned int group)
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+{
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ return group + 2;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ return 6;
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+ }
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+}
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+
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+static inline void enable_local_irq(unsigned int ip)
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+{
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+ set_c0_status(0x100 << ip);
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+ irq_enable_hazard();
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+}
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+
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+static inline void disable_local_irq(unsigned int ip)
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+{
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+ clear_c0_status(0x100 << ip);
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+ irq_disable_hazard();
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+}
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+
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+static void aruba_enable_irq(unsigned int irq_nr)
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+{
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+ unsigned long flags;
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int group, intr_bit;
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+ volatile unsigned int *addr;
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+
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+
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+ local_irq_save(flags);
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+
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+ if (ip < 0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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+ // calculate group
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ group = ip >> 5;
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+ break;
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+ }
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+
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+ // calc interrupt bit within group
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+ ip -= (group << 5);
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+ intr_bit = 1 << ip;
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ addr = intr_group_merlot[group].base_addr;
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
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+ break;
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+ }
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+ enable_local_irq(group_to_ip(group));
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+ }
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+
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+ back_to_back_c0_hazard();
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+ local_irq_restore(flags);
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+
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+}
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+
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+static void aruba_disable_irq(unsigned int irq_nr)
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+{
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+ unsigned long flags;
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int group, intr_bit, mask;
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+ volatile unsigned int *addr;
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+
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+ local_irq_save(flags);
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+
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+ if (ip < 0) {
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+ disable_local_irq(irq_nr);
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+ } else {
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+ // calculate group
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ group = ip >> 5;
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+ break;
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+ }
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+
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+ // calc interrupt bit within group
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+ ip -= group << 5;
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+ intr_bit = 1 << ip;
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MUSCAT(addr);
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+ mask |= intr_bit;
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+ WRITE_MASK_MUSCAT(addr, mask);
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+
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+ /*
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+ if there are no more interrupts enabled in this
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+ group, disable corresponding IP
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+ */
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+ if (mask == intr_group_muscat[group].mask)
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ addr = intr_group_merlot[group].base_addr;
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+ // mask intr within group
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+ mask = READ_MASK_MERLOT(addr);
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+ mask &= ~intr_bit;
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+ if (!mask)
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+ disable_local_irq(group_to_ip(group));
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+ WRITE_MASK_MERLOT(addr, mask);
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+ break;
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+ }
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+ }
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+
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+ back_to_back_c0_hazard();
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+ local_irq_restore(flags);
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+}
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+
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+static unsigned int startup_irq(unsigned int irq_nr)
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+{
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+ aruba_enable_irq(irq_nr);
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+ return 0;
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+}
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+
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+static void shutdown_irq(unsigned int irq_nr)
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+{
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+ aruba_disable_irq(irq_nr);
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+}
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+
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+static void mask_and_ack_irq(unsigned int irq_nr)
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+{
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+ aruba_disable_irq(irq_nr);
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+}
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+
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+static void end_irq(unsigned int irq_nr)
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+{
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+
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+ int ip = irq_nr - GROUP0_IRQ_BASE;
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+ unsigned int intr_bit, group;
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+ volatile unsigned int *addr;
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+
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+
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+ if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
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+ printk("warning: end_irq %d did not enable (%x)\n",
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+ irq_nr, irq_desc[irq_nr].status);
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+ /* fall through; enable the interrupt
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+ * -- It'll get stuck otherwise
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+ */
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+
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+ }
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+
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+ if (ip<0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if (irq_nr == GROUP4_IRQ_BASE + 9) idt_gpio->gpioistat &= 0xfffffdff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 10) idt_gpio->gpioistat &= 0xfffffbff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 11) idt_gpio->gpioistat &= 0xfffff7ff;
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+ else if (irq_nr == GROUP4_IRQ_BASE + 12) idt_gpio->gpioistat &= 0xffffefff;
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+
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+ group = ip >> 5;
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+
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+ // calc interrupt bit within group
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+ ip -= (group << 5);
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ addr = intr_group_muscat[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ group = 0;
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+
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+ // calc interrupt bit within group
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+ intr_bit = 1 << ip;
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+
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+ // first enable the IP mapped to this IRQ
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+ enable_local_irq(group_to_ip(group));
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+
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+ addr = intr_group_merlot[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
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+ break;
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+ }
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+ }
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+}
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+
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+static struct hw_interrupt_type aruba_irq_type = {
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+ .typename = "ARUBA",
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+ .startup = startup_irq,
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+ .shutdown = shutdown_irq,
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+ .enable = aruba_enable_irq,
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+ .disable = aruba_disable_irq,
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+ .ack = mask_and_ack_irq,
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+ .end = end_irq,
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+};
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+
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+void __init arch_init_irq(void)
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+{
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+ int i;
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+ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
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+ memset(irq_desc, 0, sizeof(irq_desc));
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+
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+ set_c0_status(0xFF00);
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+
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+ for (i = 0; i < RC32434_NR_IRQS; i++) {
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+ irq_desc[i].status = IRQ_DISABLED;
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+ irq_desc[i].action = NULL;
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+ irq_desc[i].depth = 1;
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+ irq_desc[i].handler = &aruba_irq_type;
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+ spin_lock_init(&irq_desc[i].lock);
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+ }
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+}
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+
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+/* Main Interrupt dispatcher */
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+
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+void plat_irq_dispatch(struct pt_regs *regs)
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+{
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+ unsigned int pend, group, ip;
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+ volatile unsigned int *addr;
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+ unsigned long cp0_cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
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+
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+ if (cp0_cause & CAUSEF_IP7)
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+ aruba_timer_interrupt(regs);
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+
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+ if(cp0_cause == 0) {
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+ printk("INTERRUPT(S) FIRED WHILE MASKED\n");
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+#ifdef ARUBA_DEBUG
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+ // debuging use -- figure out which interrupt(s) fired
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+ cp0_cause = read_c0_cause() & CAUSEF_IP;
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+ while (cp0_cause) {
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+ intr_bit = (31 - rc32434_clz(cp0_cause));
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+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
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+ printk(" ---> MASKED IRQ %d\n",irq_nr);
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+ cp0_cause &= ~(1 << intr_bit);
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+ }
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+#endif
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+ return;
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+ }
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if ((ip = (cp0_cause & 0x7c00))) {
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+ group = 21 - rc32434_clz(ip);
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+
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+ addr = intr_group_muscat[group].base_addr;
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+
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+ pend = READ_PEND_MUSCAT(addr);
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+ pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
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+ pend = 39 - rc32434_clz(pend);
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+ do_IRQ((group << 5) + pend, regs);
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+ }
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
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+ // Misc Interrupt
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+ group = 0;
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+ addr = intr_group_merlot[group].base_addr;
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+ pend = READ_PEND_MERLOT(addr);
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+ pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
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+ /* handle one misc interrupt at a time */
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+ while (pend)
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+ {
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+
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+ intr_bit = (31 - rc32434_clz(pend));
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+ irq_nr = intr_bit + GROUP0_IRQ_BASE;
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+
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+ do_IRQ(irq_nr, regs);
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+ pend &= ~(1 << intr_bit);
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+ }
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+ } else if (cp0_cause & 0x3c00) { // irq 2-5
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+ while (cp0_cause)
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+ {
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+
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+ intr_bit = (31 - rc32434_clz(cp0_cause));
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+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
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+
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+ do_IRQ(irq_nr, regs);
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+ cp0_cause &= ~(1 << intr_bit);
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+ }
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+ }
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+ break;
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+ }
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+}
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