bb39b8d99a
Update our copies of the brcm2708 patches to the latest rpi-3.10-y rebased against linux-3.10.y stable (3.10.32). This should hopefully make it easier for us in the future to leverage the raspberry/rpi-* branches. Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 39770
54 lines
2 KiB
Diff
54 lines
2 KiB
Diff
From 4d44d8447b13ded9c6931583938183c76b1846ed Mon Sep 17 00:00:00 2001
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From: P33M <P33M@github.com>
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Date: Sat, 13 Jul 2013 21:48:41 +0100
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Subject: [PATCH 079/174] dwc_otg: fiq: prevent FIQ thrash and incorrect state
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passing to IRQ
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In the case of a transaction to a device that had previously aborted
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due to an error, several interrupts are enabled to reset the error
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count when a device responds. This has the side-effect of making the
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FIQ thrash because the hardware will generate multiple instances of
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a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK
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on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the
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associated interrupts.
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Additionally, on non-split transactions make sure that only unmasked
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interrupts are cleared. This caused a hard-to-trigger but serious
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race condition when you had the combination of an endpoint awaiting
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error recovery and a transaction completed on an endpoint - due to
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the sequencing and timing of interrupts generated by the dwc_otg core,
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it was possible to confuse the IRQ handler.
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---
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drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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@@ -324,6 +324,27 @@ int fiq_hcintr_handle(int channel, hfnum
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}
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}
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}
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+ else
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+ {
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+ /*
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+ * If we have any of NAK, ACK, Datatlgerr active on a
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+ * non-split channel, the sole reason is to reset error
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+ * counts for a previously broken transaction. The FIQ
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+ * will thrash on NAK IN and ACK OUT in particular so
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+ * handle it "once" and allow the IRQ to do the rest.
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+ */
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+ hcint.d32 &= hcintmsk.d32;
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+ if(hcint.b.nak)
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+ {
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+ hcintmsk.b.nak = 0;
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+ FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32);
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+ }
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+ if (hcint.b.ack)
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+ {
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+ hcintmsk.b.ack = 0;
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+ FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0xc), hcintmsk.d32);
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+ }
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+ }
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// Clear the interrupt, this will also clear the HAINT bit
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FIQ_WRITE((dwc_regs_base + 0x500 + (channel * 0x20) + 0x8), hcint.d32);
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