93dd2f7211
- Rebased the patches for 4.14 - Dropped spi-qup and 0027, 0028, 0029 clk patches since it's already included in upstream. Tested on IPQ AP148 Board: 1) NOR boot and NAND boot 2) Tested USB and PCIe interfaces 3) WDOG test 4) cpu frequency scaling 5) ethernet, 2G and 5G WiFi 6) ubi sysupgrade Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
164 lines
3.9 KiB
Text
164 lines
3.9 KiB
Text
#include "qcom-ipq8064.dtsi"
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/ {
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model = "Qualcomm IPQ8065";
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compatible = "qcom,ipq8065", "qcom,ipq8064";
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qcom,pvs {
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qcom,pvs-format-a;
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qcom,speed0-pvs0-bin-v0 =
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< 1725000000 1262500 >,
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< 1400000000 1175000 >,
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< 1000000000 1100000 >,
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< 800000000 1050000 >,
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< 600000000 1000000 >,
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< 384000000 975000 >;
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qcom,speed0-pvs1-bin-v0 =
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< 1725000000 1225000 >,
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< 1400000000 1150000 >,
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< 1000000000 1075000 >,
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< 800000000 1025000 >,
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< 600000000 975000 >,
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< 384000000 950000 >;
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qcom,speed0-pvs2-bin-v0 =
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< 1725000000 1200000 >,
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< 1400000000 1125000 >,
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< 1000000000 1050000 >,
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< 800000000 1000000 >,
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< 600000000 950000 >,
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< 384000000 925000 >;
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qcom,speed0-pvs3-bin-v0 =
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< 1725000000 1175000 >,
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< 1400000000 1100000 >,
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< 1000000000 1025000 >,
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< 800000000 975000 >,
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< 600000000 925000 >,
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< 384000000 900000 >;
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qcom,speed0-pvs4-bin-v0 =
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< 1725000000 1150000 >,
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< 1400000000 1075000 >,
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< 1000000000 1000000 >,
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< 800000000 950000 >,
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< 600000000 900000 >,
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< 384000000 875000 >;
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qcom,speed0-pvs5-bin-v0 =
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< 1725000000 1100000 >,
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< 1400000000 1025000 >,
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< 1000000000 950000 >,
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< 800000000 900000 >,
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< 600000000 850000 >,
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< 384000000 825000 >;
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qcom,speed0-pvs6-bin-v0 =
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< 1725000000 1050000 >,
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< 1400000000 975000 >,
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< 1000000000 900000 >,
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< 800000000 850000 >,
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< 600000000 800000 >,
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< 384000000 775000 >;
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};
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soc: soc {
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rpm@108000 {
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regulators {
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smb208_s2a: s2a {
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regulator-min-microvolt = <775000>;
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regulator-max-microvolt = <1275000>;
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};
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smb208_s2b: s2b {
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regulator-min-microvolt = <775000>;
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regulator-max-microvolt = <1275000>;
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};
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};
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};
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ss_phy_0: phy@110f8830 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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};
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ss_phy_1: phy@100f8830 {
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rx_eq = <2>;
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tx_deamp_3_5db = <32>;
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mpll = <0xa0>;
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};
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/* Temporary fixed regulator */
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdcc1bam:dma@12402000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <0 98 0>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc3bam:dma@12182000 {
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <0 96 0>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x2000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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};
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sdcc3: sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x2000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <192000000>;
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#mmc-ddr-1_8v;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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vqmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
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dma-names = "tx", "rx";
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};
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};
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};
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};
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