02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
From 0566b74f93eaf6b2281d2605a63e06e6ba809334 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Mon, 3 Feb 2014 09:51:40 +0800
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Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
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clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Divs clocks consist of a parent factor clock with multiple outputs,
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and seperate clocks for each output. Get the name of the parent
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clock from the parent factor clock, instead of the DT node name.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Acked-by: Mike Turquette <mturquette@linaro.org>
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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drivers/clk/sunxi/clk-sunxi.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -940,7 +940,7 @@ static void __init sunxi_divs_clk_setup(
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struct divs_data *data)
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{
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struct clk_onecell_data *clk_data;
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- const char *parent = node->name;
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+ const char *parent;
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const char *clk_name;
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struct clk **clks, *pclk;
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struct clk_hw *gate_hw, *rate_hw;
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@@ -954,6 +954,7 @@ static void __init sunxi_divs_clk_setup(
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/* Set up factor clock that we will be dividing */
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pclk = sunxi_factors_clk_setup(node, data->factors);
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+ parent = __clk_get_name(pclk);
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reg = of_iomap(node, 0);
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