a8bdf2f1e0
This is needed for some new patches. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 42221
568 lines
20 KiB
Diff
568 lines
20 KiB
Diff
--- a/drivers/bcma/Makefile
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+++ b/drivers/bcma/Makefile
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@@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
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bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
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bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
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bcma-y += driver_pci.o
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+bcma-y += driver_pcie2.o
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bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
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bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
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bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
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tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
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break;
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+ case BCMA_CHIP_ID_BCM43131:
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+ case BCMA_CHIP_ID_BCM43217:
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case BCMA_CHIP_ID_BCM43227:
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case BCMA_CHIP_ID_BCM43228:
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case BCMA_CHIP_ID_BCM43428:
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--- a/drivers/bcma/driver_gpio.c
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+++ b/drivers/bcma/driver_gpio.c
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@@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c
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#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
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chip->to_irq = bcma_gpio_to_irq;
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#endif
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- chip->ngpio = 16;
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+ switch (cc->core->bus->chipinfo.id) {
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+ case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM53572:
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+ chip->ngpio = 32;
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+ break;
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+ default:
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+ chip->ngpio = 16;
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+ }
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+
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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* a random base number. */
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--- /dev/null
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+++ b/drivers/bcma/driver_pcie2.c
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@@ -0,0 +1,175 @@
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+/*
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+ * Broadcom specific AMBA
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+ * PCIe Gen 2 Core
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+ *
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+ * Copyright 2014, Broadcom Corporation
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+ * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include "bcma_private.h"
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+#include <linux/bcma/bcma.h>
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+
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+/**************************************************
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+ * R/W ops.
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+ **************************************************/
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+
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+#if 0
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+static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
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+{
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
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+ pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
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+ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
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+}
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+#endif
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+
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+static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
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+ u32 val)
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+{
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
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+}
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+
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+/**************************************************
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+ * Init.
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+ **************************************************/
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+
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+static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
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+ bool enable)
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+{
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+ u32 val;
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+
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+ /* restore back to default */
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+ val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
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+ val |= PCIE2_CLKC_DLYPERST;
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+ val &= ~PCIE2_CLKC_DISSPROMLD;
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+ if (enable) {
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+ val &= ~PCIE2_CLKC_DLYPERST;
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+ val |= PCIE2_CLKC_DISSPROMLD;
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+ }
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+ pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
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+ /* flush */
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+ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
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+}
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+
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+static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
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+{
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+ /* LTR0 */
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
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+ /* LTR1 */
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
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+ /* LTR2 */
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
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+}
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+
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+static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
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+{
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+ u8 core_rev = pcie2->core->id.rev;
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+ u32 devstsctr2;
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+
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+ if (core_rev < 2 || core_rev == 10 || core_rev > 13)
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+ return;
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+
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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+ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
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+ devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
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+ if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
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+ /* force the right LTR values */
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+ bcma_core_pcie2_set_ltr_vals(pcie2);
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+
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+ /* TODO:
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+ si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
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+
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+ /* enable the LTR */
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+ devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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+ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
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+
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+ /* set the LTR state to be active */
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
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+ PCIE2_LTR_ACTIVE);
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+ usleep_range(1000, 2000);
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+
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+ /* set the LTR state to be sleep */
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
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+ PCIE2_LTR_SLEEP);
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+ usleep_range(1000, 2000);
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+ }
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+}
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+
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+static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
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+{
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+ u8 core_rev = pcie2->core->id.rev;
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+ bool pciewar160, pciewar162;
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+
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+ pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
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+ pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
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+ core_rev == 9 || core_rev == 11;
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+
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+ if (!pciewar160 && !pciewar162)
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+ return;
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+
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+/* TODO */
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+#if 0
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+ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
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+ PCIE_DISABLE_L1CLK_GATING);
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+#if 0
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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+ PCIEGEN2_COE_PVT_TL_CTRL_0);
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+ pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
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+ ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
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+#endif
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+#endif
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+}
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+
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+static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
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+{
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
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+ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
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+}
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+
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+static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
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+{
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
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+}
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+
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+static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
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+{
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+ struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
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+ u8 core_rev = pcie2->core->id.rev;
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+ u32 alp_khz, pm_value;
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+
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+ if (core_rev <= 13) {
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+ alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
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+ pm_value = (1000000 * 2) / alp_khz;
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
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+ PCIE2_PVT_REG_PM_CLK_PERIOD);
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+ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
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+ }
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+}
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+
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+void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
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+{
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+ struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
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+ u32 tmp;
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+
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+ tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
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+ if ((tmp & 0xe) >> 1 == 2)
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+ bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
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+
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+ /* TODO: Do we need pcie_reqsize? */
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+
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+ if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
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+ bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
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+ bcma_core_pcie2_hw_ltr_war(pcie2);
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+ pciedev_crwlpciegen2(pcie2);
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+ pciedev_reg_pm_clk_period(pcie2);
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+ pciedev_crwlpciegen2_180(pcie2);
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+ pciedev_crwlpciegen2_182(pcie2);
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+}
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--- a/drivers/bcma/host_pci.c
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+++ b/drivers/bcma/host_pci.c
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@@ -279,6 +279,8 @@ static const struct pci_device_id bcma_p
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
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{ 0, },
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};
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--- a/drivers/bcma/main.c
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+++ b/drivers/bcma/main.c
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@@ -132,6 +132,7 @@ static int bcma_register_cores(struct bc
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case BCMA_CORE_CHIPCOMMON:
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case BCMA_CORE_PCI:
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case BCMA_CORE_PCIE:
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+ case BCMA_CORE_PCIE2:
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case BCMA_CORE_MIPS_74K:
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case BCMA_CORE_4706_MAC_GBIT_COMMON:
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continue;
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@@ -281,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
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bcma_core_pci_init(&bus->drv_pci[1]);
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}
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+ /* Init PCIe Gen 2 core */
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+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
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+ if (core) {
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+ bus->drv_pcie2.core = core;
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+ bcma_core_pcie2_init(&bus->drv_pcie2);
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+ }
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+
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/* Init GBIT MAC COMMON core */
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core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
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if (core) {
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--- a/drivers/bcma/sprom.c
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+++ b/drivers/bcma/sprom.c
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@@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
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SPEX(_field[7], _offset + 14, _mask, _shift); \
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} while (0)
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+static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
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+{
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+ u16 v;
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+ u8 gain;
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+
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+ v = in[SPOFF(offset)];
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+ gain = (v & mask) >> shift;
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+ if (gain == 0xFF) {
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+ gain = 8; /* If unset use 2dBm */
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+ } else {
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+ /* Q5.2 Fractional part is stored in 0xC0 */
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+ gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
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+ }
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+
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+ return (s8)gain;
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+}
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+
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static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
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{
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u16 v, o;
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@@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
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SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
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/* Extract the antenna gain values. */
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- SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
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- SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
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- SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
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- SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
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- SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
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- SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
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- SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
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- SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
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+ bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
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+ SSB_SPROM8_AGAIN01,
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+ SSB_SPROM8_AGAIN0,
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+ SSB_SPROM8_AGAIN0_SHIFT);
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+ bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
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+ SSB_SPROM8_AGAIN01,
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+ SSB_SPROM8_AGAIN1,
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+ SSB_SPROM8_AGAIN1_SHIFT);
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+ bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
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+ SSB_SPROM8_AGAIN23,
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+ SSB_SPROM8_AGAIN2,
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+ SSB_SPROM8_AGAIN2_SHIFT);
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+ bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
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+ SSB_SPROM8_AGAIN23,
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+ SSB_SPROM8_AGAIN3,
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+ SSB_SPROM8_AGAIN3_SHIFT);
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SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
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SSB_SPROM8_LEDDC_ON_SHIFT);
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@@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
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/* for these chips OTP is always available */
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present = true;
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break;
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+ case BCMA_CHIP_ID_BCM43131:
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+ case BCMA_CHIP_ID_BCM43217:
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case BCMA_CHIP_ID_BCM43227:
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case BCMA_CHIP_ID_BCM43228:
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case BCMA_CHIP_ID_BCM43428:
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -6,6 +6,7 @@
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#include <linux/bcma/bcma_driver_chipcommon.h>
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#include <linux/bcma/bcma_driver_pci.h>
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+#include <linux/bcma/bcma_driver_pcie2.h>
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#include <linux/bcma/bcma_driver_mips.h>
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#include <linux/bcma/bcma_driver_gmac_cmn.h>
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#include <linux/ssb/ssb.h> /* SPROM sharing */
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@@ -72,17 +73,17 @@ struct bcma_host_ops {
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/* Core-ID values. */
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#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
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#define BCMA_CORE_4706_CHIPCOMMON 0x500
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-#define BCMA_CORE_PCIEG2 0x501
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-#define BCMA_CORE_DMA 0x502
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-#define BCMA_CORE_SDIO3 0x503
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-#define BCMA_CORE_USB20 0x504
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-#define BCMA_CORE_USB30 0x505
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-#define BCMA_CORE_A9JTAG 0x506
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-#define BCMA_CORE_DDR23 0x507
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-#define BCMA_CORE_ROM 0x508
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-#define BCMA_CORE_NAND 0x509
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-#define BCMA_CORE_QSPI 0x50A
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-#define BCMA_CORE_CHIPCOMMON_B 0x50B
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+#define BCMA_CORE_NS_PCIEG2 0x501
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+#define BCMA_CORE_NS_DMA 0x502
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+#define BCMA_CORE_NS_SDIO3 0x503
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+#define BCMA_CORE_NS_USB20 0x504
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+#define BCMA_CORE_NS_USB30 0x505
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+#define BCMA_CORE_NS_A9JTAG 0x506
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+#define BCMA_CORE_NS_DDR23 0x507
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+#define BCMA_CORE_NS_ROM 0x508
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+#define BCMA_CORE_NS_NAND 0x509
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+#define BCMA_CORE_NS_QSPI 0x50A
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+#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
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#define BCMA_CORE_4706_SOC_RAM 0x50E
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#define BCMA_CORE_ARMCA9 0x510
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#define BCMA_CORE_4706_MAC_GBIT 0x52D
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@@ -157,6 +158,9 @@ struct bcma_host_ops {
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/* Chip IDs of PCIe devices */
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#define BCMA_CHIP_ID_BCM4313 0x4313
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#define BCMA_CHIP_ID_BCM43142 43142
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+#define BCMA_CHIP_ID_BCM43131 43131
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+#define BCMA_CHIP_ID_BCM43217 43217
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+#define BCMA_CHIP_ID_BCM43222 43222
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#define BCMA_CHIP_ID_BCM43224 43224
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#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
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#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
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@@ -333,6 +337,7 @@ struct bcma_bus {
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struct bcma_drv_cc drv_cc;
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struct bcma_drv_pci drv_pci[2];
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+ struct bcma_drv_pcie2 drv_pcie2;
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struct bcma_drv_mips drv_mips;
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struct bcma_drv_gmac_cmn drv_gmac_cmn;
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--- /dev/null
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+++ b/include/linux/bcma/bcma_driver_pcie2.h
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@@ -0,0 +1,158 @@
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+#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
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+#define LINUX_BCMA_DRIVER_PCIE2_H_
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+
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+#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
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+#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
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+#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
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+#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
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+#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
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+#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
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+#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
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+#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
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+#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
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+#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
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+#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
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+#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
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+#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
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+#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
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+#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
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+#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
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+#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
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+#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
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+#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
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+#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
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+#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
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+#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
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+#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
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+#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
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+#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
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+#define BCMA_CORE_PCIE2_DATAINTF 0x0180
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+#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
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+#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
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+#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
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+#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
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+#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
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+#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
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+#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
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+#define PCIE2_LTR_ACTIVE 2
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+#define PCIE2_LTR_ACTIVE_IDLE 1
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+#define PCIE2_LTR_SLEEP 0
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+#define PCIE2_LTR_FINAL_MASK 0x300
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+#define PCIE2_LTR_FINAL_SHIFT 8
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+#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
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+#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
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+#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
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+#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
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+#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
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+#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
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+#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
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+#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
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+#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
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+#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
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+#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
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+#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
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+#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
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+#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
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+#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
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+#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
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+#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
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+#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
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+#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
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+#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
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+#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
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+#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
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+#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
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+#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
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+#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
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+#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
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+#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
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+#define BCMA_CORE_PCIE2_OARR0 0x0D20
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+#define BCMA_CORE_PCIE2_OARR1 0x0D28
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+#define BCMA_CORE_PCIE2_OARR2 0x0D30
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+#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
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+#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
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+#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
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+#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
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+#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
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+#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
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+#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
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+#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
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+#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
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+#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
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+#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
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+#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
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+#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
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+#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
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+#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
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+#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
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+#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
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+#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
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+#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
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+#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
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+#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
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+#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
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+
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+/* PCIE gen2 config regs */
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+#define PCIE2_INTSTATUS 0x090
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+#define PCIE2_INTMASK 0x094
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+#define PCIE2_SBMBX 0x098
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+
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+#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
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+
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+#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
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+#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
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+#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
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+
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+struct bcma_drv_pcie2 {
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+ struct bcma_device *core;
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+};
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+
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+#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
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+#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
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+#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
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+#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
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+
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+#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
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+#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
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+
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+void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
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+
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+#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
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--- a/drivers/bcma/scan.c
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+++ b/drivers/bcma/scan.c
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@@ -32,17 +32,17 @@ static const struct bcma_device_id_name
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{ BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
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{ BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
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{ BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
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- { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
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- { BCMA_CORE_DMA, "DMA" },
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- { BCMA_CORE_SDIO3, "SDIO3" },
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- { BCMA_CORE_USB20, "USB 2.0" },
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- { BCMA_CORE_USB30, "USB 3.0" },
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- { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
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- { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
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- { BCMA_CORE_ROM, "ROM" },
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- { BCMA_CORE_NAND, "NAND flash controller" },
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- { BCMA_CORE_QSPI, "SPI flash controller" },
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- { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
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+ { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
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+ { BCMA_CORE_NS_DMA, "DMA" },
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+ { BCMA_CORE_NS_SDIO3, "SDIO3" },
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+ { BCMA_CORE_NS_USB20, "USB 2.0" },
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+ { BCMA_CORE_NS_USB30, "USB 3.0" },
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+ { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
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+ { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
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+ { BCMA_CORE_NS_ROM, "ROM" },
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+ { BCMA_CORE_NS_NAND, "NAND flash controller" },
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+ { BCMA_CORE_NS_QSPI, "SPI flash controller" },
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+ { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
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{ BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
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{ BCMA_CORE_AMEMC, "AMEMC (DDR)" },
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{ BCMA_CORE_ALTA, "ALTA (I2S)" },
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