02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
236 lines
6.4 KiB
Diff
236 lines
6.4 KiB
Diff
From a740d2b024c5b71c6f9989976049f03b634bb13d Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Fri, 16 May 2014 16:07:13 -0700
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Subject: [PATCH 107/182] clk: qcom: Support msm8974pro global clock control
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hardware
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A new PLL (gpll4) is added on msm8974 PRO devices to support a
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faster sdc1 clock rate. Add support for this and the two new sdcc
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cal clocks.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Mike Turquette <mturquette@linaro.org>
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---
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.../devicetree/bindings/clock/qcom,gcc.txt | 2 +
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drivers/clk/qcom/gcc-msm8974.c | 130 +++++++++++++++++++-
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include/dt-bindings/clock/qcom,gcc-msm8974.h | 4 +
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3 files changed, 130 insertions(+), 6 deletions(-)
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--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
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+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
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@@ -8,6 +8,8 @@ Required properties :
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"qcom,gcc-msm8660"
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"qcom,gcc-msm8960"
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"qcom,gcc-msm8974"
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+ "qcom,gcc-msm8974pro"
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+ "qcom,gcc-msm8974pro-ac"
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- reg : shall contain base register location and length
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- #clock-cells : shall contain 1
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--- a/drivers/clk/qcom/gcc-msm8974.c
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+++ b/drivers/clk/qcom/gcc-msm8974.c
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@@ -35,6 +35,7 @@
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#define P_XO 0
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#define P_GPLL0 1
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#define P_GPLL1 1
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+#define P_GPLL4 2
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static const u8 gcc_xo_gpll0_map[] = {
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[P_XO] = 0,
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@@ -46,6 +47,18 @@ static const char *gcc_xo_gpll0[] = {
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"gpll0_vote",
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};
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+static const u8 gcc_xo_gpll0_gpll4_map[] = {
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+ [P_XO] = 0,
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+ [P_GPLL0] = 1,
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+ [P_GPLL4] = 5,
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+};
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+
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+static const char *gcc_xo_gpll0_gpll4[] = {
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+ "xo",
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+ "gpll0_vote",
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+ "gpll4_vote",
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+};
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+
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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static struct clk_pll gpll0 = {
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@@ -138,6 +151,33 @@ static struct clk_regmap gpll1_vote = {
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},
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};
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+static struct clk_pll gpll4 = {
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+ .l_reg = 0x1dc4,
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+ .m_reg = 0x1dc8,
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+ .n_reg = 0x1dcc,
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+ .config_reg = 0x1dd4,
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+ .mode_reg = 0x1dc0,
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+ .status_reg = 0x1ddc,
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+ .status_bit = 17,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "gpll4",
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+ .parent_names = (const char *[]){ "xo" },
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+ .num_parents = 1,
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+ .ops = &clk_pll_ops,
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+ },
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+};
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+
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+static struct clk_regmap gpll4_vote = {
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+ .enable_reg = 0x1480,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gpll4_vote",
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+ .parent_names = (const char *[]){ "gpll4" },
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+ .num_parents = 1,
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+ .ops = &clk_pll_vote_ops,
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+ },
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+};
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+
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static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
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F(125000000, P_GPLL0, 1, 5, 24),
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{ }
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@@ -812,18 +852,33 @@ static const struct freq_tbl ftbl_gcc_sd
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{ }
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};
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+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
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+ F(144000, P_XO, 16, 3, 25),
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+ F(400000, P_XO, 12, 1, 4),
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+ F(20000000, P_GPLL0, 15, 1, 2),
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+ F(25000000, P_GPLL0, 12, 1, 2),
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+ F(50000000, P_GPLL0, 12, 0, 0),
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+ F(100000000, P_GPLL0, 6, 0, 0),
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+ F(192000000, P_GPLL4, 4, 0, 0),
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+ F(200000000, P_GPLL0, 3, 0, 0),
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+ F(384000000, P_GPLL4, 2, 0, 0),
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+ { }
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+};
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+
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+static struct clk_init_data sdcc1_apps_clk_src_init = {
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+ .name = "sdcc1_apps_clk_src",
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+ .parent_names = gcc_xo_gpll0,
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+ .num_parents = 2,
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+ .ops = &clk_rcg2_ops,
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+};
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+
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static struct clk_rcg2 sdcc1_apps_clk_src = {
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.cmd_rcgr = 0x04d0,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = gcc_xo_gpll0_map,
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.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
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- .clkr.hw.init = &(struct clk_init_data){
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- .name = "sdcc1_apps_clk_src",
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- .parent_names = gcc_xo_gpll0,
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- .num_parents = 2,
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- .ops = &clk_rcg2_ops,
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- },
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+ .clkr.hw.init = &sdcc1_apps_clk_src_init,
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};
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static struct clk_rcg2 sdcc2_apps_clk_src = {
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@@ -1995,6 +2050,38 @@ static struct clk_branch gcc_sdcc1_apps_
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},
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};
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+static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
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+ .halt_reg = 0x04e8,
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+ .clkr = {
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+ .enable_reg = 0x04e8,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_sdcc1_cdccal_ff_clk",
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+ .parent_names = (const char *[]){
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+ "xo"
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
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+ .halt_reg = 0x04e4,
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+ .clkr = {
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+ .enable_reg = 0x04e4,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_sdcc1_cdccal_sleep_clk",
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+ .parent_names = (const char *[]){
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+ "sleep_clk_src"
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_branch gcc_sdcc2_ahb_clk = {
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.halt_reg = 0x0508,
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.clkr = {
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@@ -2484,6 +2571,10 @@ static struct clk_regmap *gcc_msm8974_cl
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[GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
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[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
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[GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
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+ [GPLL4] = NULL,
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+ [GPLL4_VOTE] = NULL,
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+ [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
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+ [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
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};
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static const struct qcom_reset_map gcc_msm8974_resets[] = {
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@@ -2585,14 +2676,41 @@ static const struct qcom_cc_desc gcc_msm
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static const struct of_device_id gcc_msm8974_match_table[] = {
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{ .compatible = "qcom,gcc-msm8974" },
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+ { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
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+ { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
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+static void msm8974_pro_clock_override(void)
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+{
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+ sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
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+ sdcc1_apps_clk_src_init.num_parents = 3;
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+ sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
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+ sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
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+
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+ gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
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+ gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
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+ gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
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+ &gcc_sdcc1_cdccal_sleep_clk.clkr;
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+ gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
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+ &gcc_sdcc1_cdccal_ff_clk.clkr;
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+}
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+
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static int gcc_msm8974_probe(struct platform_device *pdev)
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{
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struct clk *clk;
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struct device *dev = &pdev->dev;
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+ bool pro;
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+ const struct of_device_id *id;
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+
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+ id = of_match_device(gcc_msm8974_match_table, dev);
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+ if (!id)
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+ return -ENODEV;
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+ pro = !!(id->data);
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+
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+ if (pro)
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+ msm8974_pro_clock_override();
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/* Temporary until RPM clocks supported */
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clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
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--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
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+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
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@@ -316,5 +316,9 @@
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#define GCC_CE2_CLK_SLEEP_ENA 299
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#define GCC_CE2_AXI_CLK_SLEEP_ENA 300
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#define GCC_CE2_AHB_CLK_SLEEP_ENA 301
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+#define GPLL4 302
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+#define GPLL4_VOTE 303
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+#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304
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+#define GCC_SDCC1_CDCCAL_FF_CLK 305
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#endif
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