02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
75 lines
2.6 KiB
Diff
75 lines
2.6 KiB
Diff
From 8a70c89b2fbb635a8d4fec302165343827aeed9f Mon Sep 17 00:00:00 2001
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From: Georgi Djakov <gdjakov@mm-sol.com>
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Date: Mon, 10 Mar 2014 17:37:11 +0200
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Subject: [PATCH 046/182] mmc: sdhci-msm: Qualcomm SDHCI binding documentation
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This patch adds the device-tree binding documentation for Qualcomm
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SDHCI driver. It contains the differences between the core properties
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in mmc.txt and the properties used by the sdhci-msm driver.
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Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
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Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
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Signed-off-by: Chris Ball <chris@printf.net>
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---
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.../devicetree/bindings/mmc/sdhci-msm.txt | 55 ++++++++++++++++++++
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1 file changed, 55 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
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@@ -0,0 +1,55 @@
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+* Qualcomm SDHCI controller (sdhci-msm)
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+
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+This file documents differences between the core properties in mmc.txt
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+and the properties used by the sdhci-msm driver.
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+
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+Required properties:
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+- compatible: Should contain "qcom,sdhci-msm-v4".
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+- reg: Base address and length of the register in the following order:
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+ - Host controller register map (required)
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+ - SD Core register map (required)
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+- interrupts: Should contain an interrupt-specifiers for the interrupts:
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+ - Host controller interrupt (required)
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+- pinctrl-names: Should contain only one value - "default".
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+- pinctrl-0: Should specify pin control groups used for this controller.
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+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
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+- clock-names: Should contain the following:
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+ "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
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+ "core" - SDC MMC clock (MCLK) (required)
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+ "bus" - SDCC bus voter clock (optional)
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+
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+Example:
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+
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+ sdhc_1: sdhci@f9824900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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+ interrupts = <0 123 0>;
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+ bus-width = <8>;
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+ non-removable;
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+
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+ vmmc = <&pm8941_l20>;
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+ vqmmc = <&pm8941_s3>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
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+
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+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ };
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+
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+ sdhc_2: sdhci@f98a4900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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+ interrupts = <0 125 0>;
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+ bus-width = <4>;
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+ cd-gpios = <&msmgpio 62 0x1>;
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+
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+ vmmc = <&pm8941_l21>;
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+ vqmmc = <&pm8941_l13>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
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+
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+ clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ };
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