153 lines
3.7 KiB
Diff
153 lines
3.7 KiB
Diff
From e96ef422d0095fe9ae39b03c0805a0db8ff7e382 Mon Sep 17 00:00:00 2001
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From: Jon Mason <jonmason@broadcom.com>
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Date: Tue, 13 Oct 2015 17:22:25 -0400
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Subject: [PATCH 50/50] ARM: dts: enable clock support for BCM5301X
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Replace current device tree dummy clocks with real clock support for
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Broadcom Northstar SoCs.
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Signed-off-by: Jon Mason <jonmason@broadcom.com>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++---------
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1 file changed, 69 insertions(+), 19 deletions(-)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -8,6 +8,7 @@
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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+#include <dt-bindings/clock/bcm-nsp.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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@@ -42,41 +43,48 @@
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mpcore {
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compatible = "simple-bus";
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- ranges = <0x00000000 0x19020000 0x00003000>;
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+ ranges = <0x00000000 0x19000000 0x00023000>;
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#address-cells = <1>;
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#size-cells = <1>;
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- scu@0000 {
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+ a9pll: arm_clk@00000 {
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+ #clock-cells = <0>;
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+ compatible = "brcm,nsp-armpll";
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+ clocks = <&osc>;
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+ reg = <0x00000 0x1000>;
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+ };
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+
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+ scu@20000 {
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compatible = "arm,cortex-a9-scu";
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- reg = <0x0000 0x100>;
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+ reg = <0x20000 0x100>;
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};
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- timer@0200 {
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+ timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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- reg = <0x0200 0x100>;
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+ reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&clk_periph>;
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+ clocks = <&periph_clk>;
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};
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- local-timer@0600 {
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+ local-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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- reg = <0x0600 0x100>;
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+ reg = <0x20600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&clk_periph>;
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+ clocks = <&periph_clk>;
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};
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- gic: interrupt-controller@1000 {
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+ gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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- reg = <0x1000 0x1000>,
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- <0x0100 0x100>;
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+ reg = <0x21000 0x1000>,
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+ <0x20100 0x100>;
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};
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- L2: cache-controller@2000 {
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+ L2: cache-controller@22000 {
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compatible = "arm,pl310-cache";
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- reg = <0x2000 0x1000>;
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+ reg = <0x22000 0x1000>;
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cache-unified;
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arm,shared-override;
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prefetch-data = <1>;
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@@ -94,14 +102,37 @@
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clocks {
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#address-cells = <1>;
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- #size-cells = <0>;
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+ #size-cells = <1>;
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+ ranges;
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- /* As long as we do not have a real clock driver us this
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- * fixed clock */
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- clk_periph: periph {
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+ osc: oscillator {
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+ #clock-cells = <0>;
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compatible = "fixed-clock";
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+ clock-frequency = <25000000>;
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+ };
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+
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+ iprocmed: iprocmed {
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#clock-cells = <0>;
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- clock-frequency = <400000000>;
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+ compatible = "fixed-factor-clock";
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+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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+ clock-div = <2>;
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+ clock-mult = <1>;
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+ };
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+
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+ iprocslow: iprocslow {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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+ clock-div = <4>;
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+ clock-mult = <1>;
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+ };
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+
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+ periph_clk: periph_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clocks = <&a9pll>;
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+ clock-div = <2>;
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+ clock-mult = <1>;
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};
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};
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@@ -189,4 +220,23 @@
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brcm,nand-has-wp;
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};
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+
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+ lcpll0: lcpll0@1800c100 {
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+ #clock-cells = <1>;
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+ compatible = "brcm,nsp-lcpll0";
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+ reg = <0x1800c100 0x14>;
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+ clocks = <&osc>;
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+ clock-output-names = "lcpll0", "pcie_phy", "sdio",
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+ "ddr_phy";
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+ };
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+
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+ genpll: genpll@1800c140 {
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+ #clock-cells = <1>;
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+ compatible = "brcm,nsp-genpll";
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+ reg = <0x1800c140 0x24>;
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+ clocks = <&osc>;
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+ clock-output-names = "genpll", "phy", "ethernetclk",
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+ "usbclk", "iprocfast", "sata1",
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+ "sata2";
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+ };
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};
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