71 lines
2 KiB
Diff
71 lines
2 KiB
Diff
From 54524f4531c8b262431b794fea610d81bb351c86 Mon Sep 17 00:00:00 2001
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From: Harald Welte <laforge@openmoko.org>
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Date: Tue, 21 Oct 2008 08:17:07 +0100
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Subject: [PATCH] S3C24xx NAND: allow for faster timings
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Tacls can actually be zero with some NAND flash devices, so we need
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to permit this.
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Also, the TACLS register actually specifies the actual number of
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HCLK clocks, where the TWRPH0 and TWRPH1 registers are auto-incremented
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by one HCLK clock in hardware.
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Signed-off-by: Harald Welte <laforge@openmoko.org>
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---
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drivers/mtd/nand/s3c2410.c | 13 +++++++------
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1 files changed, 7 insertions(+), 6 deletions(-)
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diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
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index 4413d76..eeb48ed 100644
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--- a/drivers/mtd/nand/s3c2410.c
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+++ b/drivers/mtd/nand/s3c2410.c
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@@ -158,6 +158,10 @@ static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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{
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int result;
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+ /* Tacls can be 0ns in some cases */
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+ if (wanted == 0)
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+ return 0;
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+
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result = (wanted * clk) / NS_IN_KHZ;
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result++;
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@@ -168,9 +172,6 @@ static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
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return -1;
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}
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- if (result < 1)
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- result = 1;
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-
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return result;
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}
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@@ -202,7 +203,7 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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twrph1 = 8;
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}
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- if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
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+ if (tacls < 0 || twrph0 < 1 || twrph1 < 1) {
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dev_err(info->device, "cannot get suitable timings\n");
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return -EINVAL;
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}
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@@ -213,14 +214,14 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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switch (info->cpu_type) {
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case TYPE_S3C2410:
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cfg = S3C2410_NFCONF_EN;
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- cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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+ cfg |= S3C2410_NFCONF_TACLS(tacls);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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break;
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case TYPE_S3C2440:
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case TYPE_S3C2412:
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- cfg = S3C2440_NFCONF_TACLS(tacls - 1);
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+ cfg = S3C2440_NFCONF_TACLS(tacls);
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cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
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--
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1.5.6.5
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