4e31b2e869
This router is based on MT7621 SoC, no wifi, no usb, nand. Works: * Boots. * Ethernet. * Switch. * Button (reset). * Flashing OpenWrt from stock firmware. * Upgrading OpenWrt. Doesn't work: * No GPIO leds. All leds are controlled by switch, but stock firmware was able to control them. * SoC has crypto engine but no open driver. * SoC has nat acceleration, but no open driver. * This router has 2MB spi flash soldered in but MT nand/spi drivers do not support pin sharing, so it is not accessable and disabled. Stock firmware could read it and it was empty. * PoE out. Router has serial pins populated. If looking at the top of the router, then counting from Eth sockets pins go as: 'GND, RX, TX, GND'. 3.3v, 57600. U-boot bootloader supports tftpboot, controlled from serial. This router has two kernel partitions: 'live' and 'backup'. They are swapped during flashing (on both stock and OpenWrt). Active partition is controlled by a flag in a factory partition. U-boot has custom command to switch active kernel partition. Kernel partitions are 'bare flash' 3MB. Stock bootloader has no UBI support. Stock rootfs is UBIFS. Flashing procedure. Stock firmware uses custom kernel patch to mount squashfs from a file that is located on UBIFS volume. This makes wiping out this volume from within stock firmware difficult. Instead this patch builds image that is flashable by stock firmware and contains initrams image (with minimal set of packages to fit into kernel partition). Once this is flashed one can reboot into initramfs OpenWrt and use sysupgrade to flash OpenWrt including rootfs into nand. Note: factory image is only built if initramfs image is enabled. Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com> SVN-Revision: 47881
119 lines
2 KiB
Text
119 lines
2 KiB
Text
#include <dt-bindings/input/input.h>
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/dts-v1/;
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#include "mt7621.dtsi"
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/ {
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compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc";
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model = "UBNT-ERX";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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palmbus@1E000000 {
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spi@b00 {
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/* This board has 2Mb spi flash soldered in and visible
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from manufacturer's firmware.
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But this SoC shares spi and nand pins,
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and current driver does't handle this sharing well */
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status = "disabled";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p80";
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reg = <1>;
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linux,modalias = "m25p80";
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "spi";
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reg = <0x0 0x200000>;
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read-only;
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};
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};
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};
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};
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nand@1e003000 {
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compatible = "mtk,mt7621-nand";
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bank-width = <2>;
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reg = <0x1e003000 0x800
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0x1e003800 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x60000>;
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read-only;
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};
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factory: partition@e0000 {
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label = "factory";
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reg = <0xe0000 0x60000>;
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};
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partition@140000 {
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label = "kernel1";
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reg = <0x140000 0x300000>;
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};
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partition@440000 {
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label = "kernel2";
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reg = <0x440000 0x300000>;
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};
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partition@740000 {
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label = "ubi";
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reg = <0x740000 0xf7c0000>;
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};
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};
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ethernet@1e100000 {
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mtd-mac-address = <&factory 0x22>;
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};
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pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
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ralink,function = "gpio";
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};
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};
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};
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sdhci@1E130000 {
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status = "disabled";
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};
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pcie@1e140000 {
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status = "disabled";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 12 1>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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