404b183aa8
Add AR9 DTS definition to be recognized by the DWC2 driver. The same driver parameters can be mostly used except that some boards seem to erroneously report OTG HNP/SRP capability of the USB HCD. Forcing the HNP/SRP off allows these boards to work with the DWC2 as well. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 46915
46 lines
1.5 KiB
Diff
46 lines
1.5 KiB
Diff
--- a/drivers/usb/dwc2/platform.c
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+++ b/drivers/usb/dwc2/platform.c
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@@ -107,6 +107,34 @@ static const struct dwc2_core_params par
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.uframe_sched = -1,
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};
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+static const struct dwc2_core_params params_ltq = {
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+ .otg_cap = 2, /* non-HNP/non-SRP */
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+ .otg_ver = -1,
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+ .dma_enable = -1,
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+ .dma_desc_enable = -1,
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+ .speed = -1,
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+ .enable_dynamic_fifo = -1,
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+ .en_multiple_tx_fifo = -1,
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+ .host_rx_fifo_size = 240, /* 240 DWORDs */
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+ .host_nperio_tx_fifo_size = 240, /* 240 DWORDs */
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+ .host_perio_tx_fifo_size = 32, /* 32 DWORDs */
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+ .max_transfer_size = -1,
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+ .max_packet_count = -1,
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+ .host_channels = -1,
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+ .phy_type = -1,
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+ .phy_utmi_width = -1,
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+ .phy_ulpi_ddr = -1,
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+ .phy_ulpi_ext_vbus = -1,
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+ .i2c_enable = -1,
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+ .ulpi_fs_ls = -1,
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+ .host_support_fs_ls_low_power = -1,
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+ .host_ls_low_power_phy_clk = -1,
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+ .ts_dline = -1,
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+ .reload_ctl = -1,
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+ .ahbcfg = -1,
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+ .uframe_sched = -1,
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+};
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+
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/**
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* dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
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* DWC_otg driver
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@@ -133,6 +161,8 @@ static int dwc2_driver_remove(struct pla
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static const struct of_device_id dwc2_of_match_table[] = {
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{ .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
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{ .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
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+ { .compatible = "lantiq,ifxhcd-arx100-dwc2", .data = ¶ms_ltq },
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+ { .compatible = "lantiq,ifxhcd-xrx200-dwc2", .data = ¶ms_ltq },
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{ .compatible = "snps,dwc2", .data = NULL },
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{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
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{},
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