7c984552ed
Hardware filtering must always be enabled as long as there is an Ethernet device registered, and use device tree for setting the link activity and buffer shifting enable/disable bit. SVN-Revision: 32486
199 lines
4.2 KiB
Text
199 lines
4.2 KiB
Text
/*
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* mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC
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*
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* Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
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*
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* Licensed under GPLv2.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Moschip MCS8140 family SoC";
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compatible = "moschip,mcs8140";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uart0;
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eth0 = ð0;
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};
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vci {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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eth0: ethernet@40084000 {
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compatible = "moschip,nuport-mac";
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reg = <0x40084000 0xd8 // mac
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0x40080000 0x58>; // dma channels
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interrupts = <4 5 29>; /* tx, rx, link */
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nuport-mac,buffer-shifting;
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nuport-mac,link-activity = <0>;
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};
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tso@40088000 {
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reg = <0x40088000 0x1c>;
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};
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i2s@4008c000 {
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compatible = "moschip,mcs814x-i2s";
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reg = <0x4008c000 0x18>;
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};
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ipsec@40094000 {
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compatible = "moschip,mcs814x-ipsec";
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reg = <0x40094000 0x1d8>;
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};
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rng@4009c000 {
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compatible = "moschip,mcs814x-rng";
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reg = <0x4009c000 0x8>;
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};
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memc@400a8000 {
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reg = <0x400a8000 0x58>;
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};
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list-proc@400ac0c0 {
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reg = <0x400ac0c0 0x38>;
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};
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pci@400b0000 {
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reg = <0x400b0000 0x44 // PCI master
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0x400d8000 0xe4>; // EEPROM emulator
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interrupts = <25>; // abort interrupt
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0 0x80000000 0x80000000 0 0x04000000 // IO
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0x42000000 0 0x90000000 0x90000000 0 0x20000000 // non-prefetch
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0x02000000 0 0xb0000000 0xb0000000 0 0x10000000>; // prefecth
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#interrupt-cells = <1>;
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interrupt-map-mask = <>;
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interrupt-map = <0 0 0 1 &intc 22 0
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0 0 0 2 &intc 23 0
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0 0 0 3 &intc 24 0
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0 0 0 4 &intc 26 0>;
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};
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gpio: gpio@400d0000 {
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compatible = "moschip,mcs814x-gpio";
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reg = <0x400d0000 0x670>;
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#gpio-cells = <2>;
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gpio-controller;
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num-gpios = <20>;
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};
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eepio: gpio@400d4000 {
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compatible = "moschip,mcs814x-gpio";
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reg = <0x400d4000 0x470>;
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#gpio-cells = <2>;
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gpio-controller;
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num-gpios = <4>;
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};
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uart0: serial@400dc000 {
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compatible = "ns16550";
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reg = <0x400dc000 0x20>;
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clock-frequency = <50000000>;
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reg-shift = <2>;
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interrupts = <21>;
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status = "okay";
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};
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intc: interrupt-controller@400e4000 {
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#interrupt-cells = <1>;
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compatible = "moschip,mcs814x-intc";
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interrupt-controller;
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interrupt-parent;
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reg = <0x400e4000 0x48>;
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};
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m2m@400e8000 {
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reg = <0x400e8000 0x24>;
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};
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eth-filters@400ec000 {
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reg = <0x400ec000 0x80>;
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};
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timer: timer@400f800c {
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compatible = "moschip,mcs814x-timer";
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interrupts = <0>;
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reg = <0x400f800c 0x8>;
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};
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watchdog@400f8014 {
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compatible = "moschip,mcs814x-wdt";
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reg = <0x400f8014 0x8>;
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};
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adc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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// 8 64MB chip-selects
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ranges = <0 0 0x00000000 0x4000000 // sdram
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1 0 0x04000000 0x4000000 // sdram
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2 0 0x08000000 0x4000000 // reserved
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3 0 0x0c000000 0x4000000 // flash/localbus
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4 0 0x10000000 0x4000000 // flash/localbus
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5 0 0x14000000 0x4000000 // flash/localbus
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6 0 0x18000000 0x4000000 // flash/localbus
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7 0 0x1c000000 0x4000000>; // flash/localbus
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sdram: memory@0,0 {
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reg = <0 0 0>;
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};
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nor: flash@7,0 {
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reg = <7 0 0x4000000>;
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compatible = "cfi-flash";
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bank-width = <1>; // 8-bit external flash
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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usb0: ehci@400fc000 {
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compatible = "moschip,mcs814x-ehci", "usb-ehci";
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reg = <0x400fc000 0x74>;
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interrupts = <2>;
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};
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usb1: ohci@400fd000 {
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compatible = "moschip,mcs814x-ohci", "ohci-le";
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reg = <0x400fd000 0x74>;
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interrupts = <11>;
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};
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usb2: ohci@400fe000 {
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compatible = "moschip,mcs814x-ohci", "ohci-le";
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reg = <0x400fe000 0x74>;
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interrupts = <12>;
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};
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usb3: otg@400ff000 {
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compatible = "moschip,msc814x-otg", "usb-otg";
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reg = <0x400ff000 0x1000>;
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};
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};
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};
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};
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