254 lines
6.4 KiB
C
254 lines
6.4 KiB
C
#ifndef IFXMIPS_SW_H
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#define IFXMIPS_SW_H
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/******************************************************************************
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**
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** FILE NAME : ifxmips_sw.h
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** PROJECT : IFXMips
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** MODULES : ETH Interface (MII0)
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**
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** DATE : 11 AUG 2005
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** AUTHOR : Wu Qi Ming
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** DESCRIPTION : ETH Interface (MII0) Driver Header File
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 11 AUG 2005 Wu Qi Ming Initiate Version
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** 23 OCT 2006 Xu Liang Add GPL header.
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*******************************************************************************/
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#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE
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#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1
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#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2
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#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3
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#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4
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#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5
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#define SET_ETH_REG SIOCDEVPRIVATE+6
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#define VLAN_TOOLS SIOCDEVPRIVATE+7
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#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8
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#define SET_VLAN_COS SIOCDEVPRIVATE+9
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#define SET_DSCP_COS SIOCDEVPRIVATE+10
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#define ENABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+11
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#define DISABLE_VLAN_CLASSIFICATION SIOCDEVPRIVATE+12
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#define VLAN_CLASS_FIRST SIOCDEVPRIVATE+13
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#define VLAN_CLASS_SECOND SIOCDEVPRIVATE+14
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#define ENABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+15
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#define DISABLE_DSCP_CLASSIFICATION SIOCDEVPRIVATE+16
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#define PASS_UNICAST_PACKETS SIOCDEVPRIVATE+17
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#define FILTER_UNICAST_PACKETS SIOCDEVPRIVATE+18
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#define KEEP_BROADCAST_PACKETS SIOCDEVPRIVATE+19
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#define DROP_BROADCAST_PACKETS SIOCDEVPRIVATE+20
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#define KEEP_MULTICAST_PACKETS SIOCDEVPRIVATE+21
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#define DROP_MULTICAST_PACKETS SIOCDEVPRIVATE+22
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/*===mac table commands==*/
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#define RESET_MAC_TABLE 0
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#define READ_MAC_ENTRY 1
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#define WRITE_MAC_ENTRY 2
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#define ADD_MAC_ENTRY 3
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/*====vlan commands===*/
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#define CHANGE_VLAN_CTRL 0
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#define READ_VLAN_ENTRY 1
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#define UPDATE_VLAN_ENTRY 2
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#define CLEAR_VLAN_ENTRY 3
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#define RESET_VLAN_TABLE 4
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#define ADD_VLAN_ENTRY 5
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/*
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** MDIO constants.
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*/
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#define MDIO_BASE_STATUS_REG 0x1
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#define MDIO_BASE_CONTROL_REG 0x0
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#define MDIO_PHY_ID_HIGH_REG 0x2
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#define MDIO_PHY_ID_LOW_REG 0x3
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#define MDIO_BC_NEGOTIATE 0x0200
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#define MDIO_BC_FULL_DUPLEX_MASK 0x0100
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#define MDIO_BC_AUTO_NEG_MASK 0x1000
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#define MDIO_BC_SPEED_SELECT_MASK 0x2000
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#define MDIO_STATUS_100_FD 0x4000
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#define MDIO_STATUS_100_HD 0x2000
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#define MDIO_STATUS_10_FD 0x1000
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#define MDIO_STATUS_10_HD 0x0800
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#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800
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#define MDIO_ADVERTISMENT_REG 0x4
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#define MDIO_ADVERT_100_FD 0x100
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#define MDIO_ADVERT_100_HD 0x080
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#define MDIO_ADVERT_10_FD 0x040
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#define MDIO_ADVERT_10_HD 0x020
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#define MDIO_LINK_UP_MASK 0x4
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#define MDIO_START 0x1
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#define MDIO_READ 0x2
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#define MDIO_WRITE 0x1
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#define MDIO_PREAMBLE 0xfffffffful
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#define PHY_RESET 0x8000
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#define AUTO_NEGOTIATION_ENABLE 0X1000
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#define AUTO_NEGOTIATION_COMPLETE 0x20
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#define RESTART_AUTO_NEGOTIATION 0X200
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/*ETOP_MDIO_CFG MASKS*/
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#define SMRST_MASK 0X2000
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#define PHYA1_MASK 0X1F00
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#define PHYA0_MASK 0XF8
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#define UMM1_MASK 0X4
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#define UMM0_MASK 0X2
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/*ETOP_MDIO_ACCESS MASKS*/
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#define MDIO_RA_MASK 0X80000000
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#define MDIO_RW_MASK 0X40000000
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/*ENET_MAC_CFG MASKS*/
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#define BP_MASK 1<<12
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#define CGEN_MASK 1<<11
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#define IFG_MASK 0x3F<<5
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#define IPAUS_MASK 1<<4
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#define EPAUS_MASK 1<<3
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#define DUPLEX_MASK 1<<2
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#define SPEED_MASK 0x2
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#define LINK_MASK 1
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/*ENETS_CoS_CFG MASKS*/
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#define VLAN_MASK 2
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#define DSCP_MASK 1
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/*ENET_CFG MASKS*/
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#define VL2_MASK 1<<29
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#define FTUC_MASK 1<<25
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#define DPBC_MASK 1<<24
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#define DPMC_MASK 1<<23
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#define PHY0_ADDR 0
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#define PHY1_ADDR 1
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#define P1M 0
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#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
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#define OK 0;
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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typedef struct mac_table_entry{
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u64 mac_address:48;
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u64 p0:1;
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u64 p1:1;
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u64 p2:1;
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u64 cr:1;
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u64 ma_st:3;
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u64 res:9;
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}_mac_table_entry;
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typedef struct IFX_Switch_VLanTableEntry{
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u32 vlan_id:12;
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u32 mp0:1;
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u32 mp1:1;
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u32 mp2:1;
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u32 v:1;
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u32 res:16;
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}_IFX_Switch_VLanTableEntry;
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typedef struct mac_table_req{
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int cmd;
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int index;
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u32 data;
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u64 entry_value;
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}_mac_table_req;
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#else //not CONFIG_CPU_LITTLE_ENDIAN
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typedef struct mac_table_entry{
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u64 mac_address:48;
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u64 p0:1;
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u64 p1:1;
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u64 p2:1;
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u64 cr:1;
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u64 ma_st:3;
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u64 res:9;
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}_mac_table_entry;
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typedef struct IFX_Switch_VLanTableEntry{
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u32 vlan_id:12;
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u32 mp0:1;
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u32 mp1:1;
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u32 mp2:1;
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u32 v:1;
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u32 res:16;
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}_IFX_Switch_VLanTableEntry;
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typedef struct mac_table_req{
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int cmd;
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int index;
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u32 data;
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u64 entry_value;
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}_mac_table_req;
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#endif //CONFIG_CPU_LITTLE_ENDIAN
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typedef struct vlan_cos_req{
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int pri;
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int cos_value;
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}_vlan_cos_req;
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typedef struct dscp_cos_req{
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int dscp;
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int cos_value;
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}_dscp_cos_req;
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typedef struct vlan_req{
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int cmd;
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int index;
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u32 data;
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u32 entry_value;
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}_vlan_req;
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typedef struct data_req{
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int index;
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u32 value;
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}_data_req;
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enum duplex
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{
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half,
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full,
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autoneg
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};
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struct switch_priv {
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struct net_device_stats stats;
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int rx_packetlen;
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u8 *rx_packetdata;
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int rx_status;
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int tx_packetlen;
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#ifdef CONFIG_NET_HW_FLOWCONTROL
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int fc_bit;
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#endif //CONFIG_NET_HW_FLOWCONTROL
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u8 *tx_packetdata;
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int tx_status;
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struct dma_device_info *dma_device;
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struct sk_buff *skb;
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spinlock_t lock;
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int mdio_phy_addr;
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int current_speed;
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int current_speed_selection;
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int rx_queue_len;
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int full_duplex;
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enum duplex current_duplex;
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};
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#endif //IFXMIPS_SW_H
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