02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
172 lines
4.2 KiB
Diff
172 lines
4.2 KiB
Diff
From 7c6525a0d5cf88f9244187fbe8ee293fa4ee43c1 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Mon, 12 May 2014 19:36:23 -0500
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Subject: [PATCH 139/182] ARM: dts: msm: Add PCIe related nodes for
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IPQ8064/AP148
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 38 ++++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 93 ++++++++++++++++++++++++++++++
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2 files changed, 131 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -21,6 +21,22 @@
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bias-disable;
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};
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ drive-strength = <2>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ drive-strength = <2>;
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+ bias-disable;
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+ };
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+ };
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+
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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@@ -80,5 +96,27 @@
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};
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};
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};
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+
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+ pci@1b500000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 3 0>;
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+
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+ ranges = <0x00000000 0 0x00000000 0x0ff00000 0 0x00100000 /* configuration space */
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+ 0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
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+ };
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+
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+ pci@1b700000 {
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+ status = "ok";
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+ reset-gpio = <&qcom_pinmux 48 0>;
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+
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+ ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000 /* configuration space */
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+ 0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -2,6 +2,7 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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@@ -246,5 +247,97 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ pci@1b500000 {
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+ compatible = "qcom,pcie-ipq8064";
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+ reg = <0x1b500000 0x1000
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+ 0x1b502000 0x80
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+ 0x1b600000 0x100
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+ >;
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+ reg-names = "base", "elbi", "parf";
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+ interrupts = <0 35 0x0
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+ 0 36 0x0
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+ 0 37 0x0
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+ 0 38 0x0
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+ 0 39 0x0>;
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+ resets = <&gcc PCIE_ACLK_RESET>,
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+ <&gcc PCIE_HCLK_RESET>,
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+ <&gcc PCIE_POR_RESET>,
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+ <&gcc PCIE_PCI_RESET>,
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+ <&gcc PCIE_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ clocks = <&gcc PCIE_A_CLK>,
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+ <&gcc PCIE_H_CLK>,
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+ <&gcc PCIE_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+ status = "disabled";
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+ };
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+
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+ pci@1b700000 {
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+ compatible = "qcom,pcie-ipq8064";
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+ reg = <0x1b700000 0x1000
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+ 0x1b702000 0x80
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+ 0x1b800000 0x100
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+ >;
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+ reg-names = "base", "elbi", "parf";
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+
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+ interrupts = <0 57 0x0
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+ 0 58 0x0
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+ 0 59 0x0
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+ 0 60 0x0
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+ 0 61 0x0>;
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+ resets = <&gcc PCIE_1_ACLK_RESET>,
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+ <&gcc PCIE_1_HCLK_RESET>,
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+ <&gcc PCIE_1_POR_RESET>,
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+ <&gcc PCIE_1_PCI_RESET>,
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+ <&gcc PCIE_1_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ clocks = <&gcc PCIE_1_A_CLK>,
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+ <&gcc PCIE_1_H_CLK>,
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+ <&gcc PCIE_1_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+ status = "disabled";
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+ };
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+
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+ pci@1b900000 {
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+ compatible = "qcom,pcie-ipq8064";
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+ reg = <0x1b900000 0x1000
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+ 0x1b902000 0x80
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+ 0x1ba00000 0x100
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+ >;
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+ reg-names = "base", "elbi", "parf";
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ device_type = "pci";
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+
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+ interrupts = <0 71 0x0
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+ 0 72 0x0
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+ 0 73 0x0
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+ 0 74 0x0
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+ 0 75 0x0>;
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+ resets = <&gcc PCIE_2_ACLK_RESET>,
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+ <&gcc PCIE_2_HCLK_RESET>,
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+ <&gcc PCIE_2_POR_RESET>,
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+ <&gcc PCIE_2_PCI_RESET>,
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+ <&gcc PCIE_2_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ clocks = <&gcc PCIE_2_A_CLK>,
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+ <&gcc PCIE_2_H_CLK>,
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+ <&gcc PCIE_2_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+ status = "disabled";
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+ };
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};
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};
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