02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
184 lines
4.6 KiB
Diff
184 lines
4.6 KiB
Diff
From 355bf7c6410f5b6e37b5c2b28ebe59bb701c42d6 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Wed, 28 May 2014 12:12:40 -0500
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Subject: [PATCH 093/182] ARM: dts: qcom: Update msm8660 device trees
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* Move SoC peripherals into an SoC container node
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* Move serial enabling into board file (qcom-msm8660-surf.dts)
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* Cleanup cpu node to match binding spec, enable-method and compatible
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should be per cpu, not part of the container
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* Add GSBI node and configuration of GSBI controller
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
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arch/arm/boot/dts/qcom-msm8660.dtsi | 115 ++++++++++++++++++-------------
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2 files changed, 78 insertions(+), 47 deletions(-)
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--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
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+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
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@@ -3,4 +3,14 @@
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/ {
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model = "Qualcomm MSM8660 SURF";
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compatible = "qcom,msm8660-surf", "qcom,msm8660";
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+
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+ soc {
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+ gsbi@19c00000 {
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+ status = "ok";
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ serial@19c40000 {
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+ status = "ok";
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+ };
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+ };
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+ };
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};
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--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
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@@ -3,6 +3,7 @@
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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+#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm MSM8660";
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@@ -12,16 +13,18 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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- compatible = "qcom,scorpion";
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- enable-method = "qcom,gcc-msm8660";
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cpu@0 {
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+ compatible = "qcom,scorpion";
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+ enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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+ compatible = "qcom,scorpion";
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+ enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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@@ -33,55 +36,73 @@
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};
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};
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- intc: interrupt-controller@2080000 {
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- compatible = "qcom,msm-8660-qgic";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- reg = < 0x02080000 0x1000 >,
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- < 0x02081000 0x1000 >;
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- };
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@2080000 {
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+ compatible = "qcom,msm-8660-qgic";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = < 0x02080000 0x1000 >,
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+ < 0x02081000 0x1000 >;
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+ };
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- timer@2000000 {
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- compatible = "qcom,scss-timer", "qcom,msm-timer";
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- interrupts = <1 0 0x301>,
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- <1 1 0x301>,
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- <1 2 0x301>;
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- reg = <0x02000000 0x100>;
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- clock-frequency = <27000000>,
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- <32768>;
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- cpu-offset = <0x40000>;
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- };
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+ timer@2000000 {
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+ compatible = "qcom,scss-timer", "qcom,msm-timer";
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+ interrupts = <1 0 0x301>,
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+ <1 1 0x301>,
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+ <1 2 0x301>;
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+ reg = <0x02000000 0x100>;
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+ clock-frequency = <27000000>,
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+ <32768>;
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+ cpu-offset = <0x40000>;
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+ };
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- msmgpio: gpio@800000 {
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- compatible = "qcom,msm-gpio";
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- reg = <0x00800000 0x4000>;
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- gpio-controller;
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- #gpio-cells = <2>;
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- ngpio = <173>;
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- interrupts = <0 16 0x4>;
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- interrupt-controller;
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- #interrupt-cells = <2>;
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- };
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+ msmgpio: gpio@800000 {
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+ compatible = "qcom,msm-gpio";
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+ reg = <0x00800000 0x4000>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ ngpio = <173>;
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+ interrupts = <0 16 0x4>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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- gcc: clock-controller@900000 {
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- compatible = "qcom,gcc-msm8660";
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- reg = <0x900000 0x4000>;
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- };
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-msm8660";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ reg = <0x900000 0x4000>;
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+ };
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- serial@19c40000 {
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- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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- reg = <0x19c40000 0x1000>,
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- <0x19c00000 0x1000>;
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- interrupts = <0 195 0x0>;
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- clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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- clock-names = "core", "iface";
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- };
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+ gsbi12: gsbi@19c00000 {
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x19c00000 0x100>;
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+ clocks = <&gcc GSBI12_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ serial@19c40000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x19c40000 0x1000>,
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+ <0x19c00000 0x1000>;
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+ interrupts = <0 195 0x0>;
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+ clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+ };
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- qcom,ssbi@500000 {
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- compatible = "qcom,ssbi";
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- reg = <0x500000 0x1000>;
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- qcom,controller-type = "pmic-arbiter";
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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};
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};
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