d9bb8326fa
This brings ssb and bcma to wireless-testing tag master-2014-12-05 In addition it also adds the ARM-BCM5301X-Add-IRQs-to-Broadcom-s-bus- axi-in-DTS-f.patch which adds the irq number in a way it is done in the mainline kernel. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 43544
58 lines
2 KiB
Diff
58 lines
2 KiB
Diff
From dec378827c4aaab6c46ecdd5fc2c3b3155d68743 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed, 24 Sep 2014 23:50:07 +0200
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Subject: [PATCH] ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS file
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IRQ support for Broadcom's bus-axi driver bcma was merged into John
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Linville's wireless tree and will show up in 3.19. This patch makes use
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of this feature in the DTS file for the the BCM5301X SoCs. I left the
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PCIe controller out, because this still needs some discussion.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 34 ++++++++++++++++++++++++++++++++++
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1 file changed, 34 insertions(+)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -101,6 +101,40 @@
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#address-cells = <1>;
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#size-cells = <1>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0x000fffff 0xffff>;
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+ interrupt-map =
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+ /* ChipCommon */
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+ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* USB 2.0 Controller */
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+ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* USB 3.0 Controller */
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+ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* Ethernet Controller 0 */
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+ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* Ethernet Controller 1 */
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+ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* Ethernet Controller 2 */
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+ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* Ethernet Controller 3 */
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+ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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+
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+ /* NAND Controller */
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+ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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+ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+
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chipcommon: chipcommon@0 {
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reg = <0x00000000 0x1000>;
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