504 lines
14 KiB
Diff
504 lines
14 KiB
Diff
From 2a7fa2dbbf68650644f807a50cc2d84ca30835c1 Mon Sep 17 00:00:00 2001
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From: Maxime Bizon <mbizon@freebox.fr>
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Date: Sun, 21 Sep 2008 04:47:13 +0200
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Subject: [PATCH] [MIPS] BCM63XX: Add PCI support.
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Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
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---
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arch/mips/bcm63xx/Kconfig | 2 +
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arch/mips/bcm63xx/setup.c | 2 +
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arch/mips/pci/Makefile | 2 +
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arch/mips/pci/fixup-bcm63xx.c | 21 +++
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arch/mips/pci/ops-bcm63xx.c | 179 +++++++++++++++++++++++
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arch/mips/pci/pci-bcm63xx.c | 178 ++++++++++++++++++++++
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arch/mips/pci/pci-bcm63xx.h | 27 ++++
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include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h | 6 +
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8 files changed, 417 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/pci/fixup-bcm63xx.c
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create mode 100644 arch/mips/pci/ops-bcm63xx.c
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create mode 100644 arch/mips/pci/pci-bcm63xx.c
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create mode 100644 arch/mips/pci/pci-bcm63xx.h
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create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
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diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
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index e6d2699..7ca370a 100644
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--- a/arch/mips/bcm63xx/Kconfig
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+++ b/arch/mips/bcm63xx/Kconfig
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@@ -3,7 +3,9 @@ menu "CPU support"
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config BCM63XX_CPU_6348
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bool "support 6348 CPU"
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+ select HW_HAS_PCI
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config BCM63XX_CPU_6358
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bool "support 6358 CPU"
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+ select HW_HAS_PCI
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endmenu
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diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
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index 55c51a9..4d8b127 100644
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--- a/arch/mips/bcm63xx/setup.c
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+++ b/arch/mips/bcm63xx/setup.c
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@@ -105,4 +105,6 @@ void __init plat_mem_setup(void)
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pm_power_off = bcm63xx_machine_halt;
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set_io_port_base(0);
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+ ioport_resource.start = 0;
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+ ioport_resource.end = ~0;
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}
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diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
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index c8c32f4..0b688a8 100644
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
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obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
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obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
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obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
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+obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
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+ ops-bcm63xx.o
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#
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# These are still pretty much in the old state, watch, go blind.
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diff --git a/arch/mips/pci/fixup-bcm63xx.c b/arch/mips/pci/fixup-bcm63xx.c
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new file mode 100644
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index 0000000..3408630
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--- /dev/null
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+++ b/arch/mips/pci/fixup-bcm63xx.c
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@@ -0,0 +1,21 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <bcm63xx_cpu.h>
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+
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+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ return bcm63xx_get_irq_number(IRQ_PCI);
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+}
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ return 0;
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+}
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diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
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new file mode 100644
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index 0000000..f8dce9d
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--- /dev/null
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+++ b/arch/mips/pci/ops-bcm63xx.c
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@@ -0,0 +1,179 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+
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+#include "pci-bcm63xx.h"
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+
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+/*
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+ * swizzle 32bits data to return only the needed part
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+ */
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+static int postprocess_read(u32 data, int where, unsigned int size)
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+{
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+ u32 ret;
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+
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+ ret = 0;
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+ switch (size) {
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+ case 1:
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+ ret = (data >> ((where & 3) << 3)) & 0xff;
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+ break;
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+ case 2:
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+ ret = (data >> ((where & 3) << 3)) & 0xffff;
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+ break;
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+ case 4:
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+ ret = data;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static int preprocess_write(u32 orig_data, u32 val, int where,
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+ unsigned int size)
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+{
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+ u32 ret;
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+
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+ ret = 0;
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+ switch (size) {
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+ case 1:
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+ ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 2:
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+ ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 4:
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+ ret = val;
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+ break;
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+ }
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+ return ret;
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+}
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+
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+/*
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+ * setup hardware for a configuration cycle with given parameters
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+ */
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+static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
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+ unsigned int devfn, int where)
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+{
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+ unsigned int slot, func, reg;
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+ u32 val;
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+
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+ slot = PCI_SLOT(devfn);
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+ func = PCI_FUNC(devfn);
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+ reg = where >> 2;
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+
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+ /* sanity check */
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+ if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
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+ return 1;
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+
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+ if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
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+ return 1;
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+
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+ if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
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+ return 1;
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+
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+ /* ok, setup config access */
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+ val = (reg << MPI_L2PCFG_REG_SHIFT);
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+ val |= (func << MPI_L2PCFG_FUNC_SHIFT);
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+ val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
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+ val |= MPI_L2PCFG_CFG_USEREG_MASK;
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+ val |= MPI_L2PCFG_CFG_SEL_MASK;
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+ /* type 0 cycle for local bus, type 1 cycle for anything else */
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+ if (type != 0) {
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+ /* FIXME: how to specify bus ??? */
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+ val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
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+ }
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+ bcm_mpi_writel(val, MPI_L2PCFG_REG);
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+
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+ return 0;
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+}
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+
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+static int bcm63xx_do_cfg_read(int type, unsigned int busn,
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+ unsigned int devfn, int where, int size,
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+ u32 *val)
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+{
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+ u32 data;
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+
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+ /* two phase cycle, first we write address, then read data at
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+ * another location, caller already has a spinlock so no need
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+ * to add one here */
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+ if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ iob();
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+ data = le32_to_cpu(__raw_readl(pci_iospace_start));
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+ /* restore IO space normal behaviour */
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+ bcm_mpi_writel(0, MPI_L2PCFG_REG);
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+
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+ *val = postprocess_read(data, where, size);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int bcm63xx_do_cfg_write(int type, unsigned int busn,
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+ unsigned int devfn, int where, int size,
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+ u32 val)
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+{
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+ u32 data;
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+
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+ /* two phase cycle, first we write address, then write data to
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+ * another location, caller already has a spinlock so no need
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+ * to add one here */
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+ if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ iob();
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+
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+ data = le32_to_cpu(__raw_readl(pci_iospace_start));
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+ data = preprocess_write(data, val, where, size);
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+
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+ __raw_writel(cpu_to_le32(data), pci_iospace_start);
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+ wmb();
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+ /* no way to know the access is done, we have to wait */
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+ udelay(500);
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+ /* restore IO space normal behaviour */
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+ bcm_mpi_writel(0, MPI_L2PCFG_REG);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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+ int type;
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+
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+ type = bus->parent ? 1 : 0;
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+
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+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return bcm63xx_do_cfg_read(type, bus->number, devfn,
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+ where, size, val);
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+}
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+
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+static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ int type;
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+
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+ type = bus->parent ? 1 : 0;
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+
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+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return bcm63xx_do_cfg_write(type, bus->number, devfn,
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+ where, size, val);
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+}
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+
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+struct pci_ops bcm63xx_pci_ops = {
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+ .read = bcm63xx_pci_read,
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+ .write = bcm63xx_pci_write
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+};
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diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
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new file mode 100644
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index 0000000..52bac8e
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--- /dev/null
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -0,0 +1,178 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <asm/bootinfo.h>
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+
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+#include "pci-bcm63xx.h"
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+
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+/* allow PCI to be disabled at runtime depending on board nvram
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+ * configuration */
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+int bcm63xx_pci_enabled = 0;
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+
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+static struct resource bcm_pci_mem_resource = {
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+ .name = "bcm63xx PCI memory space",
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+ .start = BCM_PCI_MEM_BASE_PA,
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+ .end = BCM_PCI_MEM_END_PA,
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+ .flags = IORESOURCE_MEM
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+};
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+
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+static struct resource bcm_pci_io_resource = {
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+ .name = "bcm63xx PCI IO space",
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+ .start = BCM_PCI_IO_BASE_PA,
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+ .end = BCM_PCI_IO_END_PA,
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+ .flags = IORESOURCE_IO
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+};
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+
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+struct pci_controller bcm63xx_controller = {
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+ .pci_ops = &bcm63xx_pci_ops,
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+ .io_resource = &bcm_pci_io_resource,
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+ .mem_resource = &bcm_pci_mem_resource,
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+};
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+
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+static u32 bcm63xx_int_cfg_readl(u32 reg)
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+{
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+ u32 tmp;
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+
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+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
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+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
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+ bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
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+ iob();
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+ return bcm_mpi_readl(MPI_PCICFGDATA_REG);
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+}
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+
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+static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
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+{
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+ u32 tmp;
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+
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+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
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+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
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+ bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
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+ bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
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+}
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+
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+void __iomem *pci_iospace_start;
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+
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+static int __init bcm63xx_pci_init(void)
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+{
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+ unsigned int mem_size;
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+ u32 val;
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+
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+ if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
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+ return -ENODEV;
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+
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+ if (!bcm63xx_pci_enabled)
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+ return -ENODEV;
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+
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+ /*
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+ * configuration access are done through IO space, remap 4
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+ * first bytes to access it from CPU.
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+ *
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+ * this means that no io access from CPU should happen while
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+ * we do a configuration cycle, but there's no way we can add
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+ * a spinlock for each io access, so this is currently kind of
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+ * broken on SMP.
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+ */
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+ pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
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+ if (!pci_iospace_start)
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+ return -ENOMEM;
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+
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+ /* setup local bus to PCI access (PCI memory) */
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+ val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
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+ bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
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+ bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
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+ bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
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+
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+ /* set Cardbus IDSEL (type 0 cfg access on primary bus for
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+ * this IDSEL will be done on Cardbus instead) */
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+ val = bcm_pcmcia_readl(PCMCIA_C1_REG);
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+ val &= ~PCMCIA_C1_CBIDSEL_MASK;
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+ val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
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+ bcm_pcmcia_writel(val, PCMCIA_C1_REG);
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+
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+ /* disable second access windows */
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+ bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
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+
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+ /* setup local bus to PCI access (IO memory), we have only 1
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+ * IO window for both PCI and cardbus, but it cannot handle
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+ * both at the same time, assume standard PCI for now, if
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+ * cardbus card has IO zone, PCI fixup will change window to
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+ * cardbus */
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+ val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
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+ bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
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+ bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
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+ bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
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+
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+ /* enable PCI related GPIO pins */
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+ bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
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+
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+ /* setup PCI to local bus access, used by PCI device to target
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+ * local RAM while bus mastering */
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+ bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
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+ if (BCMCPU_IS_6358())
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+ val = MPI_SP0_REMAP_ENABLE_MASK;
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+ else
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+ val = 0;
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+ bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
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+
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+ bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
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+ bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
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+
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+ mem_size = bcm63xx_get_memory_size();
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+
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+ /* 6348 before rev b0 exposes only 16 MB of RAM memory through
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+ * PCI, throw a warning if we have more memory */
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+ if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
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+ if (mem_size > (16 * 1024 * 1024))
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+ printk(KERN_WARNING "bcm63xx: this CPU "
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+ "revision cannot handle more than 16MB "
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+ "of RAM for PCI bus mastering\n");
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+ } else {
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+ /* setup sp0 range to local RAM size */
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+ bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
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+ bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
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+ }
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+
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+ /* change host bridge retry counter to infinite number of
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+ * retry, needed for some broadcom wifi cards with Silicon
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+ * Backplane bus where access to srom seems very slow */
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+ val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
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+ val &= ~REG_TIMER_RETRY_MASK;
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+ bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
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+
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+ /* enable memory decoder and bus mastering */
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+ val = bcm63xx_int_cfg_readl(PCI_COMMAND);
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+ val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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+ bcm63xx_int_cfg_writel(val, PCI_COMMAND);
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+
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+ /* enable read prefetching & disable byte swapping for bus
|
|
+ * mastering transfers */
|
|
+ val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
|
|
+ val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
|
|
+ val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
|
|
+ val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
|
|
+ val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
|
|
+ bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
|
|
+
|
|
+ /* enable pci interrupt */
|
|
+ val = bcm_mpi_readl(MPI_LOCINT_REG);
|
|
+ val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
|
|
+ bcm_mpi_writel(val, MPI_LOCINT_REG);
|
|
+
|
|
+ register_pci_controller(&bcm63xx_controller);
|
|
+
|
|
+ /* mark memory space used for IO mapping as reserved */
|
|
+ request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
|
|
+ "bcm63xx PCI IO space");
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+arch_initcall(bcm63xx_pci_init);
|
|
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
|
|
new file mode 100644
|
|
index 0000000..a6e594e
|
|
--- /dev/null
|
|
+++ b/arch/mips/pci/pci-bcm63xx.h
|
|
@@ -0,0 +1,27 @@
|
|
+#ifndef PCI_BCM63XX_H_
|
|
+#define PCI_BCM63XX_H_
|
|
+
|
|
+#include <bcm63xx_cpu.h>
|
|
+#include <bcm63xx_io.h>
|
|
+#include <bcm63xx_regs.h>
|
|
+#include <bcm63xx_dev_pci.h>
|
|
+
|
|
+/*
|
|
+ * Cardbus shares the PCI bus, but has no IDSEL, so a special id is
|
|
+ * reserved for it. If you have a standard PCI device at this id, you
|
|
+ * need to change the following definition.
|
|
+ */
|
|
+#define CARDBUS_PCI_IDSEL 0x8
|
|
+
|
|
+/*
|
|
+ * defined in ops-bcm63xx.c
|
|
+ */
|
|
+extern struct pci_ops bcm63xx_pci_ops;
|
|
+extern struct pci_ops bcm63xx_cb_ops;
|
|
+
|
|
+/*
|
|
+ * defined in pci-bcm63xx.c
|
|
+ */
|
|
+extern void __iomem *pci_iospace_start;
|
|
+
|
|
+#endif /* ! PCI_BCM63XX_H_ */
|
|
diff --git a/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
|
|
new file mode 100644
|
|
index 0000000..c549344
|
|
--- /dev/null
|
|
+++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
|
|
@@ -0,0 +1,6 @@
|
|
+#ifndef BCM63XX_DEV_PCI_H_
|
|
+#define BCM63XX_DEV_PCI_H_
|
|
+
|
|
+extern int bcm63xx_pci_enabled;
|
|
+
|
|
+#endif /* BCM63XX_DEV_PCI_H_ */
|
|
--
|
|
1.5.4.3
|
|
|