4224b52c3a
- random-bcm2708 and spi-bcm2708 have been removed. - sound-soc-bcm2708-i2s has been upstreamed as sound-soc-bcm2835-i2s. Let's keep linux 4.1 for a while, since linux 4.4 appears to have some issues with multicast traffic on RPi ethernet: https://gist.github.com/Noltari/5b1cfdecce5ed4bc08fd Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> SVN-Revision: 48266
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From fce554c6331b34458db54722cb06eb517a32b305 Mon Sep 17 00:00:00 2001
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From: Matthias Reichl <hias@horus.com>
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Date: Sun, 11 Oct 2015 15:25:51 +0200
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Subject: [PATCH 016/127] bcm2835-i2s: setup clock only if CPU is clock master
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Code ported from bcm2708-i2s driver in Raspberry Pi tree.
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RPi commit c14827ecdaa36607f6110f9ce8df96e698672191 ("bcm2708: Allow
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option card devices to be configured via DT")
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Original work by Zoltan Szenczi, committed to RPi tree by
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Phil Elwell.
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Signed-off-by: Matthias Reichl <hias@horus.com>
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---
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sound/soc/bcm/bcm2835-i2s.c | 28 +++++++++++++++++++---------
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1 file changed, 19 insertions(+), 9 deletions(-)
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--- a/sound/soc/bcm/bcm2835-i2s.c
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+++ b/sound/soc/bcm/bcm2835-i2s.c
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@@ -411,15 +411,25 @@ static int bcm2835_i2s_hw_params(struct
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divf = dividend & BCM2835_CLK_DIVF_MASK;
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}
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- /* Set clock divider */
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- regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG, BCM2835_CLK_PASSWD
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- | BCM2835_CLK_DIVI(divi)
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- | BCM2835_CLK_DIVF(divf));
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+ /* Clock should only be set up here if CPU is clock master */
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+ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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+ case SND_SOC_DAIFMT_CBS_CFS:
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+ case SND_SOC_DAIFMT_CBS_CFM:
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+ /* Set clock divider */
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+ regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG,
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+ BCM2835_CLK_PASSWD
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+ | BCM2835_CLK_DIVI(divi)
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+ | BCM2835_CLK_DIVF(divf));
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- /* Setup clock, but don't start it yet */
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- regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, BCM2835_CLK_PASSWD
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- | BCM2835_CLK_MASH(mash)
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- | BCM2835_CLK_SRC(clk_src));
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+ /* Setup clock, but don't start it yet */
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+ regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
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+ BCM2835_CLK_PASSWD
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+ | BCM2835_CLK_MASH(mash)
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+ | BCM2835_CLK_SRC(clk_src));
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+ break;
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+ default:
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+ break;
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+ }
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/* Setup the frame format */
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format = BCM2835_I2S_CHEN;
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