166 lines
4.2 KiB
Diff
166 lines
4.2 KiB
Diff
--- a/arch/mips/ath79/dev-eth.c
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+++ b/arch/mips/ath79/dev-eth.c
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@@ -198,7 +198,6 @@ void __init ath79_register_mdio(unsigned
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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case ATH79_SOC_QCA9533:
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- case ATH79_SOC_QCA9561:
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case ATH79_SOC_TP9343:
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mdio_dev = &ath79_mdio1_device;
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mdio_data = &ath79_mdio1_data;
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@@ -209,6 +208,7 @@ void __init ath79_register_mdio(unsigned
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case ATH79_SOC_AR9344:
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case ATH79_SOC_QCA9556:
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case ATH79_SOC_QCA9558:
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+ case ATH79_SOC_QCA956X:
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if (id == 0) {
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mdio_dev = &ath79_mdio0_device;
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mdio_data = &ath79_mdio0_data;
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@@ -258,7 +258,6 @@ void __init ath79_register_mdio(unsigned
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break;
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case ATH79_SOC_QCA9533:
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- case ATH79_SOC_QCA9561:
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case ATH79_SOC_TP9343:
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mdio_data->builtin_switch = 1;
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break;
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@@ -268,6 +267,11 @@ void __init ath79_register_mdio(unsigned
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mdio_data->is_ar934x = 1;
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break;
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+ case ATH79_SOC_QCA956X:
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+ if (id == 1)
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+ mdio_data->builtin_switch = 1;
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+ break;
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+
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default:
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break;
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}
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@@ -387,6 +391,16 @@ static void qca955x_set_speed_sgmii(int
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iounmap(base);
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}
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+static void qca956x_set_speed_sgmii(int speed)
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+{
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+ void __iomem *base;
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+ u32 val = ath79_get_eth_pll(0, speed);
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+
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+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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+ __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
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+ iounmap(base);
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+}
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+
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static void ath79_set_speed_dummy(int speed)
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{
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}
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@@ -517,6 +531,10 @@ struct ag71xx_switch_platform_data ath79
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#define AR934X_PLL_VAL_100 0x00000101
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#define AR934X_PLL_VAL_10 0x00001616
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+#define QCA956X_PLL_VAL_1000 0x03000000
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+#define QCA956X_PLL_VAL_100 0x00000101
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+#define QCA956X_PLL_VAL_10 0x00001919
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+
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static void __init ath79_init_eth_pll_data(unsigned int id)
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{
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struct ath79_eth_pll_data *pll_data;
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@@ -575,13 +593,18 @@ static void __init ath79_init_eth_pll_da
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case ATH79_SOC_QCA9533:
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case ATH79_SOC_QCA9556:
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case ATH79_SOC_QCA9558:
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- case ATH79_SOC_QCA9561:
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case ATH79_SOC_TP9343:
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pll_10 = AR934X_PLL_VAL_10;
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pll_100 = AR934X_PLL_VAL_100;
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pll_1000 = AR934X_PLL_VAL_1000;
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break;
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+ case ATH79_SOC_QCA956X:
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+ pll_10 = QCA956X_PLL_VAL_10;
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+ pll_100 = QCA956X_PLL_VAL_100;
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+ pll_1000 = QCA956X_PLL_VAL_1000;
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+ break;
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+
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default:
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BUG();
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}
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@@ -656,6 +679,7 @@ static int __init ath79_setup_phy_if_mod
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case ATH79_SOC_QCA9556:
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case ATH79_SOC_QCA9558:
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+ case ATH79_SOC_QCA956X:
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switch (pdata->phy_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_RGMII:
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@@ -666,11 +690,6 @@ static int __init ath79_setup_phy_if_mod
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}
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break;
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- case ATH79_SOC_QCA9561:
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- if (!pdata->phy_if_mode)
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- pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
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- break;
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-
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default:
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BUG();
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}
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@@ -699,7 +718,7 @@ static int __init ath79_setup_phy_if_mod
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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- case ATH79_SOC_QCA9561:
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+ case ATH79_SOC_QCA956X:
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case ATH79_SOC_TP9343:
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pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
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break;
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@@ -1032,7 +1051,6 @@ void __init ath79_register_eth(unsigned
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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- case ATH79_SOC_QCA9561:
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case ATH79_SOC_TP9343:
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if (id == 0) {
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pdata->reset_bit = AR933X_RESET_GE0_MAC |
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@@ -1100,6 +1118,34 @@ void __init ath79_register_eth(unsigned
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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+ case ATH79_SOC_QCA956X:
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+ if (id == 0) {
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+ pdata->reset_bit = QCA955X_RESET_GE0_MAC |
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+ QCA955X_RESET_GE0_MDIO;
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+ if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
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+ pdata->set_speed = qca956x_set_speed_sgmii;
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+ else
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+ /* FIXME */
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+ pdata->set_speed = ath79_set_speed_dummy;
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+ } else {
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+ pdata->reset_bit = QCA955X_RESET_GE1_MAC |
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+ QCA955X_RESET_GE1_MDIO;
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+ /* FIXME */
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+ pdata->set_speed = ath79_set_speed_dummy;
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+ }
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+
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+ pdata->ddr_flush = ath79_ddr_no_flush;
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+ pdata->has_gbit = 1;
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+ pdata->is_ar724x = 1;
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+
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+ if (!pdata->fifo_cfg1)
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+ pdata->fifo_cfg1 = 0x0010ffff;
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+ if (!pdata->fifo_cfg2)
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+ pdata->fifo_cfg2 = 0x015500aa;
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+ if (!pdata->fifo_cfg3)
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+ pdata->fifo_cfg3 = 0x01f00140;
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+ break;
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+
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default:
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BUG();
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}
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@@ -1140,7 +1186,6 @@ void __init ath79_register_eth(unsigned
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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case ATH79_SOC_QCA9533:
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- case ATH79_SOC_QCA9561:
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case ATH79_SOC_TP9343:
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pdata->mii_bus_dev = &ath79_mdio1_device.dev;
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break;
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