f0a5f24217
- two upstreamed patches removed - compile tested all targets using 4.1 - run tested ar71xx Signed-off-by: Roman Yeryomin <roman@advem.lv> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47694
144 lines
3.9 KiB
Diff
144 lines
3.9 KiB
Diff
From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001
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From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
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Date: Mon, 8 Jun 2015 20:29:20 +0800
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Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver
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binding
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This patch adds device tree binding document for MT8173 cpufreq driver.
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Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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---
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.../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 127 ++++++++++++++++++++
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1 file changed, 127 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
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@@ -0,0 +1,127 @@
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+
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+Mediatek MT8173 cpufreq driver
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+-------------------
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+
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+Mediatek MT8173 cpufreq driver for CPU frequency scaling.
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+
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+Required properties:
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+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
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+- clock-names: Should contain the following:
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+ "cpu" - The multiplexer for clock input of CPU cluster.
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+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
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+ source (usually MAINPLL) when the original CPU PLL is under
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+ transition and not stable yet.
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+- operating-points: Table of frequencies and voltage CPU could be transitioned into,
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+ Frequency should be in KHz units and voltage should be in microvolts.
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+- proc-supply: Regulator for Vproc of CPU cluster.
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+
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+Optional properties:
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+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
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+ needs to do "voltage trace" to step by step scale up/down Vproc and
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+ Vsram to fit SoC specific needs. When absent, the voltage scaling
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+ flow is handled by hardware, hence no software "voltage trace" is
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+ needed.
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+
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+Example:
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+--------
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x000>;
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+ enable-method = "psci";
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+ cpu-idle-states = <&CPU_SLEEP_0>;
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+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 507000 859000
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+ 702000 908000
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+ 1001000 983000
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+ 1105000 1009000
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+ 1183000 1028000
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+ 1404000 1083000
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+ 1508000 1109000
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+ 1573000 1125000
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+ >;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x001>;
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+ enable-method = "psci";
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+ cpu-idle-states = <&CPU_SLEEP_0>;
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+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 507000 859000
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+ 702000 908000
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+ 1001000 983000
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+ 1105000 1009000
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+ 1183000 1028000
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+ 1404000 1083000
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+ 1508000 1109000
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+ 1573000 1125000
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+ >;
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+ };
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+
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+ cpu2: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x100>;
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+ enable-method = "psci";
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+ cpu-idle-states = <&CPU_SLEEP_0>;
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+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 507000 828000
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+ 702000 867000
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+ 1001000 927000
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+ 1209000 968000
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+ 1404000 1007000
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+ 1612000 1049000
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+ 1807000 1089000
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+ 1989000 1125000
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+ >;
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+ };
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+
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+ cpu3: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x101>;
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+ enable-method = "psci";
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+ cpu-idle-states = <&CPU_SLEEP_0>;
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+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 507000 828000
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+ 702000 867000
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+ 1001000 927000
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+ 1209000 968000
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+ 1404000 1007000
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+ 1612000 1049000
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+ 1807000 1089000
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+ 1989000 1125000
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+ >;
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+ };
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+
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+ &cpu0 {
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+ proc-supply = <&mt6397_vpca15_reg>;
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+ };
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+
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+ &cpu1 {
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+ proc-supply = <&mt6397_vpca15_reg>;
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+ };
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+
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+ &cpu2 {
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+ proc-supply = <&da9211_vcpu_reg>;
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+ sram-supply = <&mt6397_vsramca7_reg>;
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+ };
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+
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+ &cpu3 {
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+ proc-supply = <&da9211_vcpu_reg>;
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+ sram-supply = <&mt6397_vsramca7_reg>;
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+ };
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