Felix Fietkau 6bb7409e5a cns3xxx: Fix laguna arm11mpcore watchdog ... The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where all mpcore-wdt boards point the driver base too. I believe this is wrong because 0x600 is aliased to the timer/watchdog of the 'current CPU' where 0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus if your timer/watchdog application is switching between CPU's it can end up writing to the wrong CPU's registers which results in random board resets from watchdog timeouts etc. This patch forces the timer/watchdog driver to use CPU0's registers always. Its my opinion that other mpcore-wdt boards should be doing the same thing. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 33683		2012-10-10 11:38:58 +00:00
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imagebuilder	derive system from hostcc to allow building inside a chroot	2012-08-22 15:07:32 +00:00
linux	cns3xxx: Fix laguna arm11mpcore watchdog	2012-10-10 11:38:58 +00:00
sdk	derive system from hostcc to allow building inside a chroot	2012-08-22 15:07:32 +00:00
toolchain	derive system from hostcc to allow building inside a chroot	2012-08-22 15:07:32 +00:00
Config.in	target: add a feature flag for RTC support	2012-05-17 15:28:09 +00:00
Makefile	target: do not make target/*/install depend on target/*/compile - removes one redundant kernel build dir call on target/install	2012-06-06 17:24:05 +00:00