openwrtv3/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch
John Crispin 6b775f4517 ipq806x: add hwspinlock support
This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field

We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 46655
2015-08-17 06:17:47 +00:00

80 lines
2.3 KiB
Diff

--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -364,15 +364,21 @@
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};
@@ -405,15 +411,21 @@
clocks = <&gcc PCIE_1_A_CLK>,
<&gcc PCIE_1_H_CLK>,
- <&gcc PCIE_1_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_1_PHY_CLK>,
+ <&gcc PCIE_1_AUX_CLK>,
+ <&gcc PCIE_1_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_1_ACLK_RESET>,
<&gcc PCIE_1_HCLK_RESET>,
<&gcc PCIE_1_POR_RESET>,
<&gcc PCIE_1_PCI_RESET>,
- <&gcc PCIE_1_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_1_PHY_RESET>,
+ <&gcc PCIE_1_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};
@@ -446,15 +458,21 @@
clocks = <&gcc PCIE_2_A_CLK>,
<&gcc PCIE_2_H_CLK>,
- <&gcc PCIE_2_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_2_PHY_CLK>,
+ <&gcc PCIE_2_AUX_CLK>,
+ <&gcc PCIE_2_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_2_ACLK_RESET>,
<&gcc PCIE_2_HCLK_RESET>,
<&gcc PCIE_2_POR_RESET>,
<&gcc PCIE_2_PCI_RESET>,
- <&gcc PCIE_2_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_2_PHY_RESET>,
+ <&gcc PCIE_2_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
status = "disabled";
};