7903a9219c
A newer clk and cpufreq drivers for ipq806x platform had been sent upstream. A change that i have noticed is that now it's possible to set min, cur and max frequencies from sysfs (previously it was bugged and caused nothing). Following patches are removed: - 0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch - seems it was dropped from the patchset by current committer. - 0044-clk-qcom-krait-Remove-CLK_IS_ROOT.patch - already applied to the driver itself in the corresponding patch. - 0057-clk-qcom-Add-regmap-mux-div-clocks-support.patch - seem to be irrelevant to ipq806x. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
129 lines
3.4 KiB
Diff
129 lines
3.4 KiB
Diff
From patchwork Fri Dec 8 09:42:24 2017
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
Subject: [v4,06/12] clk: qcom: Add IPQ806X's HFPLLs
|
|
From: Sricharan R <sricharan@codeaurora.org>
|
|
X-Patchwork-Id: 10102047
|
|
Message-Id: <1512726150-7204-7-git-send-email-sricharan@codeaurora.org>
|
|
To: mturquette@baylibre.com, sboyd@codeaurora.org,
|
|
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
|
|
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
|
viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
|
|
Cc: sricharan@codeaurora.org
|
|
Date: Fri, 8 Dec 2017 15:12:24 +0530
|
|
|
|
From: Stephen Boyd <sboyd@codeaurora.org>
|
|
|
|
Describe the HFPLLs present on IPQ806X devices.
|
|
|
|
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
---
|
|
drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 82 insertions(+)
|
|
|
|
--- a/drivers/clk/qcom/gcc-ipq806x.c
|
|
+++ b/drivers/clk/qcom/gcc-ipq806x.c
|
|
@@ -30,6 +30,7 @@
|
|
#include "clk-pll.h"
|
|
#include "clk-rcg.h"
|
|
#include "clk-branch.h"
|
|
+#include "clk-hfpll.h"
|
|
#include "reset.h"
|
|
|
|
static struct clk_pll pll0 = {
|
|
@@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = {
|
|
},
|
|
};
|
|
|
|
+static struct hfpll_data hfpll0_data = {
|
|
+ .mode_reg = 0x3200,
|
|
+ .l_reg = 0x3208,
|
|
+ .m_reg = 0x320c,
|
|
+ .n_reg = 0x3210,
|
|
+ .config_reg = 0x3204,
|
|
+ .status_reg = 0x321c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3214,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll0 = {
|
|
+ .d = &hfpll0_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll0",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
|
|
+};
|
|
+
|
|
+static struct hfpll_data hfpll1_data = {
|
|
+ .mode_reg = 0x3240,
|
|
+ .l_reg = 0x3248,
|
|
+ .m_reg = 0x324c,
|
|
+ .n_reg = 0x3250,
|
|
+ .config_reg = 0x3244,
|
|
+ .status_reg = 0x325c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3314,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll1 = {
|
|
+ .d = &hfpll1_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll1",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
|
|
+};
|
|
+
|
|
+static struct hfpll_data hfpll_l2_data = {
|
|
+ .mode_reg = 0x3300,
|
|
+ .l_reg = 0x3308,
|
|
+ .m_reg = 0x330c,
|
|
+ .n_reg = 0x3310,
|
|
+ .config_reg = 0x3304,
|
|
+ .status_reg = 0x331c,
|
|
+ .config_val = 0x7845c665,
|
|
+ .droop_reg = 0x3314,
|
|
+ .droop_val = 0x0108c000,
|
|
+ .min_rate = 600000000UL,
|
|
+ .max_rate = 1800000000UL,
|
|
+};
|
|
+
|
|
+static struct clk_hfpll hfpll_l2 = {
|
|
+ .d = &hfpll_l2_data,
|
|
+ .clkr.hw.init = &(struct clk_init_data){
|
|
+ .parent_names = (const char *[]){ "pxo" },
|
|
+ .num_parents = 1,
|
|
+ .name = "hfpll_l2",
|
|
+ .ops = &clk_ops_hfpll,
|
|
+ .flags = CLK_IGNORE_UNUSED,
|
|
+ },
|
|
+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
|
|
+};
|
|
+
|
|
static struct clk_pll pll14 = {
|
|
.l_reg = 0x31c4,
|
|
.m_reg = 0x31c8,
|
|
@@ -2801,6 +2880,9 @@ static struct clk_regmap *gcc_ipq806x_cl
|
|
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
|
|
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
|
|
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
|
|
+ [PLL9] = &hfpll0.clkr,
|
|
+ [PLL10] = &hfpll1.clkr,
|
|
+ [PLL12] = &hfpll_l2.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
|