2b1c6b21b5
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
126 lines
4.7 KiB
Diff
126 lines
4.7 KiB
Diff
From cb182bb6180c57b28636669a613861023fd8f03d Mon Sep 17 00:00:00 2001
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From: Mario Kleiner <mario.kleiner.de@gmail.com>
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Date: Wed, 18 May 2016 14:02:46 +0200
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Subject: [PATCH] drm/vc4: Make pageflip completion handling more robust.
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Protect both the setup of the pageflip event and the
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latching of the new requested displaylist head pointer
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by the event lock, so we can't get into a situation
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where vc4_atomic_flush latches the new display list via
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HVS_WRITE, then immediately gets preempted before queueing
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the pageflip event, then the page-flip completes in hw and
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the vc4_crtc_handle_page_flip() runs and no-ops due to
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lack of a pending pageflip event, then vc4_atomic_flush
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continues and only then queues the pageflip event - after
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the page flip handling already no-oped. This would cause
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flip completion handling only at the next vblank - one
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frame too late.
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In vc4_crtc_handle_page_flip() check the actual DL head
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pointer in SCALER_DISPLACTX against the requested pointer
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for page flip to make sure that the flip actually really
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completed in the current vblank and doesn't get deferred
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to the next one because the DL head pointer was written
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a bit too late into SCALER_DISPLISTX, after start of
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vblank, and missed the boat. This avoids handling a
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pageflip completion too early - one frame too early.
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According to Eric, DL head pointer updates which were
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written into the HVS DISPLISTX reg get committed to hardware
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at the last pixel of active scanout. Our vblank interrupt
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handler, as triggered by PV_INT_VFP_START irq, gets to run
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earliest at the first pixel of HBLANK at the end of the
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last scanline of active scanout, ie. vblank irq handling
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runs at least 1 pixel duration after a potential pageflip
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completion happened in hardware.
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This ordering of events in the hardware, together with the
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lock protection and SCALER_DISPLACTX sampling of this patch,
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guarantees that pageflip completion handling only runs at
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exactly the vblank irq of actual pageflip completion in all
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cases.
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Background info from Eric about the relative timing of
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HVS, PV's and trigger points for interrupts, DL updates:
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https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
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Tested on RPi 2B with hardware timing measurement equipment
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and shown to no longer complete flips too early or too late.
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Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 56d1fe0979dc9b73c1c12ee07722ac380d42a0c4)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 28 ++++++++++++++++++----------
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drivers/gpu/drm/vc4/vc4_regs.h | 4 ++++
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2 files changed, 22 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -465,14 +465,6 @@ static void vc4_crtc_atomic_flush(struct
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WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
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- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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- vc4_state->mm.start);
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-
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- if (debug_dump_regs) {
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- DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
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- vc4_hvs_dump_state(dev);
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- }
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-
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if (crtc->state->event) {
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unsigned long flags;
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@@ -482,8 +474,20 @@ static void vc4_crtc_atomic_flush(struct
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spin_lock_irqsave(&dev->event_lock, flags);
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vc4_crtc->event = crtc->state->event;
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- spin_unlock_irqrestore(&dev->event_lock, flags);
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crtc->state->event = NULL;
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+
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+ HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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+ vc4_state->mm.start);
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+
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+ spin_unlock_irqrestore(&dev->event_lock, flags);
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+ } else {
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+ HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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+ vc4_state->mm.start);
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+ }
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+
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+ if (debug_dump_regs) {
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+ DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
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+ vc4_hvs_dump_state(dev);
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}
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}
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@@ -509,10 +513,14 @@ static void vc4_crtc_handle_page_flip(st
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{
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struct drm_crtc *crtc = &vc4_crtc->base;
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struct drm_device *dev = crtc->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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+ u32 chan = vc4_crtc->channel;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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- if (vc4_crtc->event) {
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+ if (vc4_crtc->event &&
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+ (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
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drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
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vc4_crtc->event = NULL;
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drm_crtc_vblank_put(crtc);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -343,6 +343,10 @@
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#define SCALER_DISPLACT0 0x00000030
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#define SCALER_DISPLACT1 0x00000034
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#define SCALER_DISPLACT2 0x00000038
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+#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
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+ (x) * (SCALER_DISPLACT1 - \
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+ SCALER_DISPLACT0))
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+
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#define SCALER_DISPCTRL0 0x00000040
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# define SCALER_DISPCTRLX_ENABLE BIT(31)
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# define SCALER_DISPCTRLX_RESET BIT(30)
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