584d7c53bd
This commit introduces new subtarget for Marvell EBU Armada Cortex A53
processor based devices.
The first device is Globalscale ESPRESSObin. Some hardware specs:
SoC: Marvell Armada 3700LP (88F3720) dual core ARM Cortex A53
processor up to 1.2GHz
RAM: 512MB, 1GB or 2GB DDR3
Storage: SATA interface
µSD card slot with footprint for an optional 4GB EMMC
4MB SPI NOR flash for bootloader
Ethernet: Topaz Networking Switch (88E6341) with 3x GbE ports
Connectors: USB 3.0
USB 2.0
µUSB port connected to PL2303SA (USB to serial bridge
controller) for UART access
Expansion: 2x 46-pin GPIO headers for accessories and shields with
I2C, GPIOs, PWM, UART, SPI, MMC, etc
MiniPCIe slot
Misc: Reset button, JTAG interface
Currently booting only from µSD card is supported.
The boards depending on date of dispatch can come with various U-Boot
versions. For the newest version 2017.03-armada-17.10 no manual
intervention should be needed to boot OpenWrt image. For the older ones
it's necessary to modify default U-Boot environment:
1. Interrupt boot process to run U-Boot command line,
2. Run following commands:
(for version 2017.03-armada-17.06 and 2017.03-armada-17.08)
setenv bootcmd "load mmc 0:1 0x4d00000 boot.scr; source 0x4d00000"
saveenv
(for version 2015.01-armada-17.02 and 2015.01-armada-17.04)
setenv bootargs "console=ttyMV0,115200 root=/dev/mmcblk0p2 rw rootwait"
setenv bootcmd "ext4load mmc 0:1 ${fdt_addr} armada-3720-espressobin.dtb; ext4load mmc 0:1 ${kernel_addr} Image; booti ${kernel_addr} - ${fdt_addr}"
saveenv
3. Poweroff, insert SD card with OpenWrt image, boot and enjoy.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
137 lines
4.7 KiB
Diff
137 lines
4.7 KiB
Diff
From patchwork Thu Sep 28 12:58:34 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,
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3/7] PCI: aardvark: set host and device to the same MAX payload size
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819587
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Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:34 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Victor Gu <xigu@marvell.com>
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Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
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subsystem will not align the MAX payload size between the host and the
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device. This patch ensures that the host and device have the same MAX
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payload size, fixing a number of problems with various PCIe devices.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -30,8 +30,10 @@
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#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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#define PCIE_CORE_LINK_TRAINING BIT(5)
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@@ -297,7 +299,8 @@ static void advk_pcie_setup_hw(struct ad
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/* Set PCIe Device Control and Status 1 PF0 register */
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reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
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- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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@@ -879,6 +882,58 @@ out_release_res:
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return err;
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}
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+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
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+{
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+ u8 *smpss = data;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ if (*smpss > dev->pcie_mpss)
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+ *smpss = dev->pcie_mpss;
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+
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+ return 0;
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+}
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+
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+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
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+{
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+ int mps;
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+
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+ if (!dev)
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+ return 0;
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+
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+ if (!pci_is_pcie(dev))
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+ return 0;
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+
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+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
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+ pcie_set_mps(dev, mps);
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
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+{
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+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
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+ u32 reg;
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+
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+ /* Find the minimal supported MAX payload size */
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+ advk_pcie_find_smpss(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
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+
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+ /* Configure RC MAX payload size */
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+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
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+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
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+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
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+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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+
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+ /* Configure device MAX payload size */
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+ advk_pcie_bus_configure_mps(bus->self, &smpss);
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+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
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+}
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+
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static int advk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -952,6 +1007,9 @@ static int advk_pcie_probe(struct platfo
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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+ /* Configure the MAX pay load size */
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+ advk_pcie_configure_mps(bus, pcie);
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+
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pci_bus_add_devices(bus);
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return 0;
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}
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