9300eda00f
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>
77 lines
2.9 KiB
Diff
77 lines
2.9 KiB
Diff
From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:26:27 +0100
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Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
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types
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Use the same functions as the legacy code
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
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1 file changed, 22 insertions(+), 17 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
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#ifdef CONFIG_OF
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static void __init ath79_clocks_init_dt(struct device_node *np)
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{
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- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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-}
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-
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-CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
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-CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
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-CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
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-CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
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-
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-static void __init ath79_clocks_init_dt_ng(struct device_node *np)
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-{
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struct clk *ref_clk;
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void __iomem *pll_base;
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@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
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goto err_clk;
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}
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- if (of_device_is_compatible(np, "qca,ar9130-pll"))
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+ if (of_device_is_compatible(np, "qca,ar7100-pll"))
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+ ar71xx_clocks_init(pll_base);
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+ else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
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+ of_device_is_compatible(np, "qca,ar9130-pll"))
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ar724x_clocks_init(pll_base);
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else if (of_device_is_compatible(np, "qca,ar9330-pll"))
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ar933x_clocks_init(pll_base);
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- else {
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- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
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- goto err_iounmap;
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- }
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+ else if (of_device_is_compatible(np, "qca,ar9340-pll"))
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+ ar934x_clocks_init(pll_base);
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+ else if (of_device_is_compatible(np, "qca,qca9530-pll"))
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+ qca953x_clocks_init(pll_base);
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+ else if (of_device_is_compatible(np, "qca,qca9550-pll"))
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+ qca955x_clocks_init(pll_base);
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+ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
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+ qca956x_clocks_init(pll_base);
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if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
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pr_err("%pOF: could not register clk provider\n", np);
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@@ -714,6 +711,14 @@ err_iounmap:
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err_clk:
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clk_put(ref_clk);
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}
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-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
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-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
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+
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+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
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+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
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+
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#endif
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