53c474abbd
This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin <john@phrozen.org>
43 lines
1.3 KiB
Diff
43 lines
1.3 KiB
Diff
From 5a8496923bafc4350f51b26964fdc3252a09fd79 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Mon, 5 Mar 2018 11:35:29 +0100
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Subject: [PATCH 14/27] MIPS: ath79: finetune cpu-overrides
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
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index 0089a740e5ae..026ad90c8ac0 100644
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--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
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+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
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@@ -36,6 +36,7 @@
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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+#define cpu_has_rixi 0
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 1
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@@ -43,6 +44,7 @@
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#define cpu_has_mips64r2 0
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#define cpu_has_mipsmt 0
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+#define cpu_has_userlocal 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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@@ -51,5 +53,9 @@
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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+#define cpu_has_vtag_icache 0
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+#define cpu_has_dc_aliases 1
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+#define cpu_has_ic_fills_f_dc 0
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+#define cpu_has_pindexed_dcache 0
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#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
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--
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2.11.0
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