529d527e2c
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> SVN-Revision: 48449
338 lines
12 KiB
Diff
338 lines
12 KiB
Diff
--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -185,7 +185,7 @@ u32 bcma_chipco_watchdog_timer_set(struc
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ticks = 2;
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else if (ticks > maxt)
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ticks = maxt;
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- bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
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} else {
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struct bcma_bus *bus = cc->core->bus;
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -15,44 +15,44 @@
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u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
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void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
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void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
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void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
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void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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- bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
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- bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
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- bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
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+ bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
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+ bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
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@@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
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{
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u32 ilp_ctl, alp_hz;
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- if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
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+ if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
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BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
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return 0;
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- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
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- BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
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+ BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
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usleep_range(1000, 2000);
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- ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
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+ ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
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ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
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- bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
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alp_hz = ilp_ctl * 32768 / 4;
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return (alp_hz + 50000) / 100000 * 100;
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@@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
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mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
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BCMA_RES_4314_MACPHY_CLK_AVAIL);
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- bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
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- bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
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bcma_wait_value(cc->core, BCMA_CLKCTLST,
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BCMA_CLKCTLST_HAVEHT, 0, 20000);
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break;
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@@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
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/* Flush */
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if (cc->pmu.rev >= 2)
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- bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
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+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
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/* TODO: Do we need to update OTP? */
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}
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@@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
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/* Set the resource masks. */
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if (min_msk)
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- bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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if (max_msk)
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- bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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/*
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* Add some delay; allow resources to come up and settle.
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@@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
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void bcma_pmu_early_init(struct bcma_drv_cc *cc)
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{
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+ struct bcma_bus *bus = cc->core->bus;
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u32 pmucap;
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- pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
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+ if (cc->core->id.rev >= 35 &&
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+ cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
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+ cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
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+ if (!cc->pmu.core)
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+ bcma_warn(bus, "Couldn't find expected PMU core");
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+ }
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+ if (!cc->pmu.core)
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+ cc->pmu.core = cc->core;
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+
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+ pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
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cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
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- bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
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- cc->pmu.rev, pmucap);
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+ bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
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+ pmucap);
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}
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void bcma_pmu_init(struct bcma_drv_cc *cc)
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{
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if (cc->pmu.rev == 1)
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- bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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- ~BCMA_CC_PMU_CTL_NOILPONW);
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+ bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
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+ ~BCMA_CC_PMU_CTL_NOILPONW);
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else
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- bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
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- BCMA_CC_PMU_CTL_NOILPONW);
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+ bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
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+ BCMA_CC_PMU_CTL_NOILPONW);
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bcma_pmu_pll_init(cc);
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bcma_pmu_resources_init(cc);
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@@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
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static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value)
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{
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
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}
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void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
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@@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
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bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
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/* RMW only the P1 divider */
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
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- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
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tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
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/* RMW only the int feedback divider */
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
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BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
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- tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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+ tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
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tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
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tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
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- bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
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tmp = BCMA_CC_PMU_CTL_PLL_UPD;
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break;
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@@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
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break;
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}
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- tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
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- bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
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+ tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
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+ bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
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}
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EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
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--- a/drivers/bcma/driver_chipcommon_sflash.c
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+++ b/drivers/bcma/driver_chipcommon_sflash.c
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@@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
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{ "M25P32", 0x15, 0x10000, 64, },
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{ "M25P64", 0x16, 0x10000, 128, },
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{ "M25FL128", 0x17, 0x10000, 256, },
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+ { "MX25L25635F", 0x18, 0x10000, 512, },
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{ NULL },
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};
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--- a/drivers/bcma/scan.c
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+++ b/drivers/bcma/scan.c
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@@ -98,6 +98,9 @@ static const struct bcma_device_id_name
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{ BCMA_CORE_SHIM, "SHIM" },
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{ BCMA_CORE_PCIE2, "PCIe Gen2" },
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{ BCMA_CORE_ARM_CR4, "ARM CR4" },
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+ { BCMA_CORE_GCI, "GCI" },
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+ { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
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+ { BCMA_CORE_ARM_CA7, "ARM CA7" },
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{ BCMA_CORE_DEFAULT, "Default" },
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};
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@@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
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switch (core->id.id) {
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case BCMA_CORE_4706_MAC_GBIT_COMMON:
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case BCMA_CORE_NS_CHIPCOMMON_B:
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+ case BCMA_CORE_PMU:
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+ case BCMA_CORE_GCI:
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/* Not used yet: case BCMA_CORE_OOB_ROUTER: */
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break;
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default:
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--- a/drivers/net/wireless/b43/main.c
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+++ b/drivers/net/wireless/b43/main.c
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@@ -1216,10 +1216,10 @@ void b43_wireless_core_phy_pll_reset(str
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case B43_BUS_BCMA:
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bcma_cc = &dev->dev->bdev->bus->drv_cc;
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- bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
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- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
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- bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
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- bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
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+ bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
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+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
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+ bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
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+ bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
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break;
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#endif
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#ifdef CONFIG_B43_SSB
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--- a/include/linux/bcma/bcma.h
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+++ b/include/linux/bcma/bcma.h
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@@ -151,6 +151,8 @@ struct bcma_host_ops {
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#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
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#define BCMA_CORE_USB30_DEV 0x83D
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#define BCMA_CORE_ARM_CR4 0x83E
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+#define BCMA_CORE_GCI 0x840
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+#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
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#define BCMA_CORE_ARM_CA7 0x847
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#define BCMA_CORE_SYS_MEM 0x849
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#define BCMA_CORE_DEFAULT 0xFFF
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -217,6 +217,11 @@
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#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
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#define BCMA_CC_CLKDIV_UART 0x000000FF
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#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
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+#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
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+#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
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+#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
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+#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
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+#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
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#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
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#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
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#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
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@@ -351,12 +356,12 @@
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#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
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#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
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#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
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-#define BCMA_CC_CHIPCTL_ADDR 0x0650
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-#define BCMA_CC_CHIPCTL_DATA 0x0654
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-#define BCMA_CC_REGCTL_ADDR 0x0658
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-#define BCMA_CC_REGCTL_DATA 0x065C
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-#define BCMA_CC_PLLCTL_ADDR 0x0660
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-#define BCMA_CC_PLLCTL_DATA 0x0664
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+#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
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+#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
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+#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
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+#define BCMA_CC_PMU_REGCTL_DATA 0x065C
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+#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
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+#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
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#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
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#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
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#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
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@@ -566,6 +571,7 @@
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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struct bcma_chipcommon_pmu {
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+ struct bcma_device *core; /* Can be separated core or just ChipCommon one */
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u8 rev; /* PMU revision */
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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@@ -662,6 +668,19 @@ struct bcma_drv_cc_b {
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#define bcma_cc_maskset32(cc, offset, mask, set) \
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bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
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+/* PMU registers access */
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+#define bcma_pmu_read32(cc, offset) \
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+ bcma_read32((cc)->pmu.core, offset)
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+#define bcma_pmu_write32(cc, offset, val) \
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+ bcma_write32((cc)->pmu.core, offset, val)
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+
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+#define bcma_pmu_mask32(cc, offset, mask) \
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+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
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+#define bcma_pmu_set32(cc, offset, set) \
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+ bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
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+#define bcma_pmu_maskset32(cc, offset, mask, set) \
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+ bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
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+
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extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
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extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
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