7a58972680
The current uboot default config for the A13 SOM erroneously enables support for the AXP209 power regulator IC which is not present on the board. This superfluous support module sets an incorrect initial clock frequency and confuses the kernel, ultimately leading to a boot failure later on. Properly disable the PMIC support and enable the EHCI support by translating the deprecated SYS_EXTRA_OPTIONS values into proper SUNXI_NO_PMIC and USB_EHCI_HCD symbols respectively. Also rename 002-add-olimex-a13-som.diff to 002-add-olimex-a13-som.patch and refresh the remaining patches of the series while we're at it. Reported-by: Mario Fischer <mario-fischer@web.de> Signed-off-by: Jo-Philipp Wich <jo@mein.io>
38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From 730d2f3a41c5ccae71b5008fffdf697d143be68c Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Wed, 16 Mar 2016 20:44:51 +0100
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Subject: [PATCH] sunxi: Fix clock_twi_onoff for sun6i
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The clock_sun6i.c implementation was not deasserting the reset for
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the regular i2c controllers, this commit fixes this.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Ian Campbell <ijc@hellion.org.uk>
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---
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arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 11 ++++++++---
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1 file changed, 8 insertions(+), 3 deletions(-)
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--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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@@ -100,13 +100,18 @@ int clock_twi_onoff(int port, int state)
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return 0;
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}
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- /* set the apb clock gate for twi */
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- if (state)
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+ /* set the apb clock gate and reset for twi */
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+ if (state) {
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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- else
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+ setbits_le32(&ccm->apb2_reset_cfg,
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+ 1 << (APB2_RESET_TWI_SHIFT + port));
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+ } else {
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+ clrbits_le32(&ccm->apb2_reset_cfg,
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+ 1 << (APB2_RESET_TWI_SHIFT + port));
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clrbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
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+ }
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return 0;
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}
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