682 lines
18 KiB
Diff
682 lines
18 KiB
Diff
From 7e7944c484954ff7b5d53047194e59bfffd1540a Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Mon, 25 Sep 2017 12:20:55 +0800
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Subject: [PATCH] rtc: support layerscape
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This is a integrated patch for layerscape rtc support.
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/rtc/rtc-pcf85263.c | 665 +++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 665 insertions(+)
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create mode 100644 drivers/rtc/rtc-pcf85263.c
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--- /dev/null
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+++ b/drivers/rtc/rtc-pcf85263.c
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@@ -0,0 +1,665 @@
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+/*
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+ * rtc-pcf85263 Driver for the NXP PCF85263 RTC
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+ * Copyright 2016 Parkeon
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/mutex.h>
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+#include <linux/rtc.h>
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+#include <linux/i2c.h>
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+#include <linux/bcd.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/regmap.h>
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+
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+
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+#define DRV_NAME "rtc-pcf85263"
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+
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+/* Quartz capacitance */
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+#define PCF85263_QUARTZCAP_7pF 0
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+#define PCF85263_QUARTZCAP_6pF 1
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+#define PCF85263_QUARTZCAP_12p5pF 2
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+
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+/* Quartz drive strength */
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+#define PCF85263_QUARTZDRIVE_NORMAL 0
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+#define PCF85263_QUARTZDRIVE_LOW 1
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+#define PCF85263_QUARTZDRIVE_HIGH 2
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+
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+
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+#define PCF85263_REG_RTC_SC 0x01 /* Seconds */
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+#define PCF85263_REG_RTC_SC_OS BIT(7) /* Oscilator stopped flag */
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+
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+#define PCF85263_REG_RTC_MN 0x02 /* Minutes */
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+#define PCF85263_REG_RTC_HR 0x03 /* Hours */
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+#define PCF85263_REG_RTC_DT 0x04 /* Day of month 1-31 */
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+#define PCF85263_REG_RTC_DW 0x05 /* Day of week 0-6 */
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+#define PCF85263_REG_RTC_MO 0x06 /* Month 1-12 */
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+#define PCF85263_REG_RTC_YR 0x07 /* Year 0-99 */
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+
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+#define PCF85263_REG_ALM1_SC 0x08 /* Seconds */
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+#define PCF85263_REG_ALM1_MN 0x09 /* Minutes */
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+#define PCF85263_REG_ALM1_HR 0x0a /* Hours */
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+#define PCF85263_REG_ALM1_DT 0x0b /* Day of month 1-31 */
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+#define PCF85263_REG_ALM1_MO 0x0c /* Month 1-12 */
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+
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+#define PCF85263_REG_ALM_CTL 0x10
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+#define PCF85263_REG_ALM_CTL_ALL_A1E 0x1f /* sec,min,hr,day,mon alarm 1 */
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+
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+#define PCF85263_REG_OSC 0x25
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+#define PCF85263_REG_OSC_CL_MASK (BIT(0) | BIT(1))
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+#define PCF85263_REG_OSC_CL_SHIFT 0
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+#define PCF85263_REG_OSC_OSCD_MASK (BIT(2) | BIT(3))
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+#define PCF85263_REG_OSC_OSCD_SHIFT 2
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+#define PCF85263_REG_OSC_LOWJ BIT(4)
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+#define PCF85263_REG_OSC_12H BIT(5)
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+
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+#define PCF85263_REG_PINIO 0x27
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+#define PCF85263_REG_PINIO_INTAPM_MASK (BIT(0) | BIT(1))
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+#define PCF85263_REG_PINIO_INTAPM_SHIFT 0
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+#define PCF85263_INTAPM_INTA (0x2 << PCF85263_REG_PINIO_INTAPM_SHIFT)
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+#define PCF85263_INTAPM_HIGHZ (0x3 << PCF85263_REG_PINIO_INTAPM_SHIFT)
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+#define PCF85263_REG_PINIO_TSPM_MASK (BIT(2) | BIT(3))
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+#define PCF85263_REG_PINIO_TSPM_SHIFT 2
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+#define PCF85263_TSPM_DISABLED (0x0 << PCF85263_REG_PINIO_TSPM_SHIFT)
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+#define PCF85263_TSPM_INTB (0x1 << PCF85263_REG_PINIO_TSPM_SHIFT)
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+#define PCF85263_REG_PINIO_CLKDISABLE BIT(7)
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+
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+#define PCF85263_REG_FUNCTION 0x28
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+#define PCF85263_REG_FUNCTION_COF_MASK 0x7
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+#define PCF85263_REG_FUNCTION_COF_OFF 0x7 /* No clock output */
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+
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+#define PCF85263_REG_INTA_CTL 0x29
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+#define PCF85263_REG_INTB_CTL 0x2A
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+#define PCF85263_REG_INTx_CTL_A1E BIT(4) /* Alarm 1 */
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+#define PCF85263_REG_INTx_CTL_ILP BIT(7) /* 0=pulse, 1=level */
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+
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+#define PCF85263_REG_FLAGS 0x2B
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+#define PCF85263_REG_FLAGS_A1F BIT(5)
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+
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+#define PCF85263_REG_RAM_BYTE 0x2c
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+
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+#define PCF85263_REG_STOPENABLE 0x2e
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+#define PCF85263_REG_STOPENABLE_STOP BIT(0)
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+
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+#define PCF85263_REG_RESET 0x2f /* Reset command */
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+#define PCF85263_REG_RESET_CMD_CPR 0xa4 /* Clear prescaler */
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+
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+#define PCF85263_MAX_REG 0x2f
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+
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+#define PCF85263_HR_PM BIT(5)
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+
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+enum pcf85263_irqpin {
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+ PCF85263_IRQPIN_NONE,
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+ PCF85263_IRQPIN_INTA,
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+ PCF85263_IRQPIN_INTB
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+};
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+
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+static const char *const pcf85263_irqpin_names[] = {
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+ [PCF85263_IRQPIN_NONE] = "None",
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+ [PCF85263_IRQPIN_INTA] = "INTA",
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+ [PCF85263_IRQPIN_INTB] = "INTB"
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+};
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+
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+struct pcf85263 {
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+ struct device *dev;
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+ struct rtc_device *rtc;
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+ struct regmap *regmap;
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+ enum pcf85263_irqpin irq_pin;
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+ int irq;
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+ bool mode_12h;
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+};
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+
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+/*
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+ * Helpers to convert 12h to 24h and vice versa.
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+ * Values in register are stored in BCD with a PM flag in bit 5
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+ *
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+ * 23:00 <=> 11PM <=> 0x31
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+ * 00:00 <=> 12AM <=> 0x12
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+ * 01:00 <=> 1AM <=> 0x01
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+ * 12:00 <=> 12PM <=> 0x32
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+ * 13:00 <=> 1PM <=> 0x21
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+ */
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+static int pcf85263_bcd12h_to_bin24h(int regval)
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+{
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+ int hr = bcd2bin(regval & 0x1f);
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+ bool pm = regval & PCF85263_HR_PM;
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+
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+ if (hr == 12)
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+ return pm ? 12 : 0;
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+
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+ return pm ? hr + 12 : hr;
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+}
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+
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+static int pcf85263_bin24h_to_bcd12h(int hr24)
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+{
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+ bool pm = hr24 >= 12;
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+ int hr12 = hr24 % 12;
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+
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+ if (!hr12)
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+ hr12++;
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+
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+ return bin2bcd(hr12) | pm ? 0 : PCF85263_HR_PM;
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+}
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+
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+static int pcf85263_read_time(struct device *dev, struct rtc_time *tm)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+ const int first = PCF85263_REG_RTC_SC;
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+ const int last = PCF85263_REG_RTC_YR;
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+ const int len = last - first + 1;
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+ u8 regs[len];
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+ u8 hr_reg;
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+ int ret;
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+
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+ ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
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+ if (ret)
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+ return ret;
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+
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+ if (regs[PCF85263_REG_RTC_SC - first] & PCF85263_REG_RTC_SC_OS) {
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+ dev_warn(dev, "Oscillator stop detected, date/time is not reliable.\n");
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+ return -EINVAL;
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+ }
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+
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+ tm->tm_sec = bcd2bin(regs[PCF85263_REG_RTC_SC - first] & 0x7f);
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+ tm->tm_min = bcd2bin(regs[PCF85263_REG_RTC_MN - first] & 0x7f);
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+
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+ hr_reg = regs[PCF85263_REG_RTC_HR - first];
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+ if (pcf85263->mode_12h)
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+ tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
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+ else
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+ tm->tm_hour = bcd2bin(hr_reg & 0x3f);
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+
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+ tm->tm_mday = bcd2bin(regs[PCF85263_REG_RTC_DT - first]);
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+ tm->tm_wday = bcd2bin(regs[PCF85263_REG_RTC_DW - first]);
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+ tm->tm_mon = bcd2bin(regs[PCF85263_REG_RTC_MO - first]) - 1;
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+ tm->tm_year = bcd2bin(regs[PCF85263_REG_RTC_YR - first]);
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+
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+ tm->tm_year += 100; /* Assume 21st century */
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+
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+ return 0;
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+}
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+
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+static int pcf85263_set_time(struct device *dev, struct rtc_time *tm)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+
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+ /*
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+ * Before setting time need to stop RTC and disable prescaler
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+ * Do this all in a single I2C transaction exploiting wraparound
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+ * as described in data sheet.
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+ * This means that the array below must be in register order
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+ */
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+ u8 regs[] = {
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+ PCF85263_REG_STOPENABLE_STOP, /* STOP */
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+ PCF85263_REG_RESET_CMD_CPR, /* Disable prescaler */
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+ /* Wrap around to register 0 (1/100s) */
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+ 0, /* 1/100s always zero. */
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+ bin2bcd(tm->tm_sec),
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+ bin2bcd(tm->tm_min),
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+ bin2bcd(tm->tm_hour), /* 24-hour */
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+ bin2bcd(tm->tm_mday),
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+ bin2bcd(tm->tm_wday + 1),
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+ bin2bcd(tm->tm_mon + 1),
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+ bin2bcd(tm->tm_year % 100)
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+ };
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+ int ret;
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+
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+ ret = regmap_bulk_write(pcf85263->regmap, PCF85263_REG_STOPENABLE,
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+ regs, sizeof(regs));
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+ if (ret)
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+ return ret;
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+
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+ /* As we have set the time in 24H update the hardware for that */
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+ if (pcf85263->mode_12h) {
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+ pcf85263->mode_12h = false;
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+ ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_OSC,
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+ PCF85263_REG_OSC_12H, 0);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ /* Start it again */
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+ return regmap_write(pcf85263->regmap, PCF85263_REG_STOPENABLE, 0);
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+}
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+
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+static int pcf85263_enable_alarm(struct pcf85263 *pcf85263, bool enable)
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+{
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+ int reg;
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+ int ret;
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+
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+ ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_ALM_CTL,
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+ PCF85263_REG_ALM_CTL_ALL_A1E,
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+ enable ? PCF85263_REG_ALM_CTL_ALL_A1E : 0);
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+ if (ret)
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+ return ret;
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+
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+ switch (pcf85263->irq_pin) {
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+ case PCF85263_IRQPIN_NONE:
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+ return 0;
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+
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+ case PCF85263_IRQPIN_INTA:
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+ reg = PCF85263_REG_INTA_CTL;
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+ break;
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+
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+ case PCF85263_IRQPIN_INTB:
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+ reg = PCF85263_REG_INTB_CTL;
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return regmap_update_bits(pcf85263->regmap, reg,
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+ PCF85263_REG_INTx_CTL_A1E,
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+ enable ? PCF85263_REG_INTx_CTL_A1E : 0);
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+}
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+
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+static int pcf85263_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+ struct rtc_time *tm = &alarm->time;
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+ const int first = PCF85263_REG_ALM1_SC;
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+ const int last = PCF85263_REG_ALM1_MO;
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+ const int len = last - first + 1;
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+ u8 regs[len];
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+ u8 hr_reg;
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+ unsigned int regval;
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+ int ret;
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+
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+ ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
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+ if (ret)
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+ return ret;
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+
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+ tm->tm_sec = bcd2bin(regs[PCF85263_REG_ALM1_SC - first] & 0x7f);
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+ tm->tm_min = bcd2bin(regs[PCF85263_REG_ALM1_MN - first] & 0x7f);
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+
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+ hr_reg = regs[PCF85263_REG_ALM1_HR - first];
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+ if (pcf85263->mode_12h)
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+ tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
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+ else
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+ tm->tm_hour = bcd2bin(hr_reg & 0x3f);
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+
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+ tm->tm_mday = bcd2bin(regs[PCF85263_REG_ALM1_DT - first]);
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+ tm->tm_mon = bcd2bin(regs[PCF85263_REG_ALM1_MO - first]) - 1;
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+ tm->tm_year = -1;
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+ tm->tm_wday = -1;
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+
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+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_ALM_CTL, ®val);
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+ if (ret)
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+ return ret;
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+ alarm->enabled = !!(regval & PCF85263_REG_ALM_CTL_ALL_A1E);
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+
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+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
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+ if (ret)
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+ return ret;
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+ alarm->pending = !!(regval & PCF85263_REG_FLAGS_A1F);
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+
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+ return 0;
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+}
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+
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+static int pcf85263_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+ struct rtc_time *tm = &alarm->time;
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+ const int first = PCF85263_REG_ALM1_SC;
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+ const int last = PCF85263_REG_ALM1_MO;
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+ const int len = last - first + 1;
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+ u8 regs[len];
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+ int ret;
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+
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+ /* Disable alarm comparison during update */
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+ ret = pcf85263_enable_alarm(pcf85263, false);
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+ if (ret)
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+ return ret;
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+
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+ /* Clear any pending alarm (write 0=>clr, 1=>no change) */
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+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
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+ (unsigned int)(~PCF85263_REG_FLAGS_A1F));
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+ if (ret)
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+ return ret;
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+
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+ /* Set the alarm time registers */
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+ regs[PCF85263_REG_ALM1_SC - first] = bin2bcd(tm->tm_sec);
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+ regs[PCF85263_REG_ALM1_MN - first] = bin2bcd(tm->tm_min);
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+ regs[PCF85263_REG_ALM1_HR - first] = pcf85263->mode_12h ?
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+ pcf85263_bin24h_to_bcd12h(tm->tm_hour) :
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+ bin2bcd(tm->tm_hour);
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+ regs[PCF85263_REG_ALM1_DT - first] = bin2bcd(tm->tm_mday);
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+ regs[PCF85263_REG_ALM1_MO - first] = bin2bcd(tm->tm_mon + 1);
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+
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+ ret = regmap_bulk_write(pcf85263->regmap, first, regs, sizeof(regs));
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+ if (ret)
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+ return ret;
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+
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+ if (alarm->enabled)
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+ ret = pcf85263_enable_alarm(pcf85263, true);
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+
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+ return ret;
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+}
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+
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+static int pcf85263_alarm_irq_enable(struct device *dev, unsigned int enable)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+
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+ return pcf85263_enable_alarm(pcf85263, !!enable);
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+}
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+
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+static irqreturn_t pcf85263_irq(int irq, void *data)
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+{
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+ struct pcf85263 *pcf85263 = data;
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+ unsigned int regval;
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+ int ret;
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+
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+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
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+ if (ret)
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+ return IRQ_NONE;
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+
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+ if (regval & PCF85263_REG_FLAGS_A1F) {
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+ regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
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+ (unsigned int)(~PCF85263_REG_FLAGS_A1F));
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+
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+ rtc_update_irq(pcf85263->rtc, 1, RTC_IRQF | RTC_AF);
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+
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+ return IRQ_HANDLED;
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+ }
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+
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+ return IRQ_NONE;
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+}
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+
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+static int pcf85263_check_osc_stopped(struct pcf85263 *pcf85263)
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+{
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+ unsigned int regval;
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+ int ret;
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+
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+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_RTC_SC, ®val);
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+ if (ret)
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+ return ret;
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+
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+ ret = regval & PCF85263_REG_RTC_SC_OS ? 1 : 0;
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+ if (ret)
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+ dev_warn(pcf85263->dev, "Oscillator stop detected, date/time is not reliable.\n");
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+
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+ return ret;
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+}
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+
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+#ifdef CONFIG_RTC_INTF_DEV
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+static int pcf85263_ioctl(struct device *dev,
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+ unsigned int cmd, unsigned long arg)
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+{
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+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
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+ int ret;
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+
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+ switch (cmd) {
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|
+ case RTC_VL_READ:
|
|
+ ret = pcf85263_check_osc_stopped(pcf85263);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ if (copy_to_user((void __user *)arg, &ret, sizeof(int)))
|
|
+ return -EFAULT;
|
|
+ return 0;
|
|
+
|
|
+ case RTC_VL_CLR:
|
|
+ return regmap_update_bits(pcf85263->regmap,
|
|
+ PCF85263_REG_RTC_SC,
|
|
+ PCF85263_REG_RTC_SC_OS, 0);
|
|
+ default:
|
|
+ return -ENOIOCTLCMD;
|
|
+ }
|
|
+}
|
|
+#else
|
|
+#define pcf85263_ioctl NULL
|
|
+#endif
|
|
+
|
|
+static int pcf85263_init_hw(struct pcf85263 *pcf85263)
|
|
+{
|
|
+ struct device_node *np = pcf85263->dev->of_node;
|
|
+ unsigned int regval;
|
|
+ u32 propval;
|
|
+ int ret;
|
|
+
|
|
+ /* Determine if oscilator has been stopped (probably low power) */
|
|
+ ret = pcf85263_check_osc_stopped(pcf85263);
|
|
+ if (ret < 0) {
|
|
+ /* Log here since this is the first hw access on probe */
|
|
+ dev_err(pcf85263->dev, "Unable to read register\n");
|
|
+
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ /* Determine 12/24H mode */
|
|
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_OSC, ®val);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ pcf85263->mode_12h = !!(regval & PCF85263_REG_OSC_12H);
|
|
+
|
|
+ /* Set oscilator register */
|
|
+ regval &= ~PCF85263_REG_OSC_12H; /* keep current 12/24 h setting */
|
|
+
|
|
+ propval = PCF85263_QUARTZCAP_12p5pF;
|
|
+ of_property_read_u32(np, "quartz-load-capacitance", &propval);
|
|
+ regval |= ((propval << PCF85263_REG_OSC_CL_SHIFT)
|
|
+ & PCF85263_REG_OSC_CL_MASK);
|
|
+
|
|
+ propval = PCF85263_QUARTZDRIVE_NORMAL;
|
|
+ of_property_read_u32(np, "quartz-drive-strength", &propval);
|
|
+ regval |= ((propval << PCF85263_REG_OSC_OSCD_SHIFT)
|
|
+ & PCF85263_REG_OSC_OSCD_MASK);
|
|
+
|
|
+ if (of_property_read_bool(np, "quartz-low-jitter"))
|
|
+ regval |= PCF85263_REG_OSC_LOWJ;
|
|
+
|
|
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_OSC, regval);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ /* Set function register (RTC mode, 1s tick, clock output static) */
|
|
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_FUNCTION,
|
|
+ PCF85263_REG_FUNCTION_COF_OFF);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ /* Set all interrupts to disabled, level mode */
|
|
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTA_CTL,
|
|
+ PCF85263_REG_INTx_CTL_ILP);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTB_CTL,
|
|
+ PCF85263_REG_INTx_CTL_ILP);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ /* Setup IO pin config register */
|
|
+ regval = PCF85263_REG_PINIO_CLKDISABLE;
|
|
+ switch (pcf85263->irq_pin) {
|
|
+ case PCF85263_IRQPIN_INTA:
|
|
+ regval |= (PCF85263_INTAPM_INTA | PCF85263_TSPM_DISABLED);
|
|
+ break;
|
|
+ case PCF85263_IRQPIN_INTB:
|
|
+ regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_INTB);
|
|
+ break;
|
|
+ case PCF85263_IRQPIN_NONE:
|
|
+ regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_DISABLED);
|
|
+ break;
|
|
+ }
|
|
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_PINIO, regval);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static const struct rtc_class_ops rtc_ops = {
|
|
+ .ioctl = pcf85263_ioctl,
|
|
+ .read_time = pcf85263_read_time,
|
|
+ .set_time = pcf85263_set_time,
|
|
+ .read_alarm = pcf85263_read_alarm,
|
|
+ .set_alarm = pcf85263_set_alarm,
|
|
+ .alarm_irq_enable = pcf85263_alarm_irq_enable,
|
|
+};
|
|
+
|
|
+static const struct regmap_config pcf85263_regmap_cfg = {
|
|
+ .reg_bits = 8,
|
|
+ .val_bits = 8,
|
|
+ .max_register = PCF85263_MAX_REG,
|
|
+};
|
|
+
|
|
+/*
|
|
+ * On some boards the interrupt line may not be wired to the CPU but only to
|
|
+ * a power supply circuit.
|
|
+ * In that case no interrupt will be specified in the device tree but the
|
|
+ * wakeup-source DT property may be used to enable wakeup programming in
|
|
+ * sysfs
|
|
+ */
|
|
+static bool pcf85263_can_wakeup_machine(struct pcf85263 *pcf85263)
|
|
+{
|
|
+ return pcf85263->irq ||
|
|
+ of_property_read_bool(pcf85263->dev->of_node, "wakeup-source");
|
|
+}
|
|
+
|
|
+static int pcf85263_probe(struct i2c_client *client,
|
|
+ const struct i2c_device_id *id)
|
|
+{
|
|
+ struct device *dev = &client->dev;
|
|
+ struct pcf85263 *pcf85263;
|
|
+ int ret;
|
|
+
|
|
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
|
|
+ I2C_FUNC_SMBUS_BYTE_DATA |
|
|
+ I2C_FUNC_SMBUS_I2C_BLOCK))
|
|
+ return -ENODEV;
|
|
+
|
|
+ pcf85263 = devm_kzalloc(dev, sizeof(*pcf85263), GFP_KERNEL);
|
|
+ if (!pcf85263)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ pcf85263->dev = dev;
|
|
+ pcf85263->irq = client->irq;
|
|
+ dev_set_drvdata(dev, pcf85263);
|
|
+
|
|
+ pcf85263->regmap = devm_regmap_init_i2c(client, &pcf85263_regmap_cfg);
|
|
+ if (IS_ERR(pcf85263->regmap)) {
|
|
+ ret = PTR_ERR(pcf85263->regmap);
|
|
+ dev_err(dev, "regmap allocation failed (%d)\n", ret);
|
|
+
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ /* Determine which interrupt pin the board uses */
|
|
+ if (pcf85263_can_wakeup_machine(pcf85263)) {
|
|
+ if (of_property_match_string(dev->of_node,
|
|
+ "interrupt-names", "INTB") >= 0)
|
|
+ pcf85263->irq_pin = PCF85263_IRQPIN_INTB;
|
|
+ else
|
|
+ pcf85263->irq_pin = PCF85263_IRQPIN_INTA;
|
|
+ } else {
|
|
+ pcf85263->irq_pin = PCF85263_IRQPIN_NONE;
|
|
+ }
|
|
+
|
|
+ ret = pcf85263_init_hw(pcf85263);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ if (pcf85263->irq) {
|
|
+ ret = devm_request_threaded_irq(dev, pcf85263->irq, NULL,
|
|
+ pcf85263_irq,
|
|
+ IRQF_ONESHOT,
|
|
+ dev->driver->name, pcf85263);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "irq %d unavailable (%d)\n",
|
|
+ pcf85263->irq, ret);
|
|
+ pcf85263->irq = 0;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (pcf85263_can_wakeup_machine(pcf85263))
|
|
+ device_init_wakeup(dev, true);
|
|
+
|
|
+ pcf85263->rtc = devm_rtc_device_register(dev, dev->driver->name,
|
|
+ &rtc_ops, THIS_MODULE);
|
|
+ ret = PTR_ERR_OR_ZERO(pcf85263->rtc);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ /* We cannot support UIE mode if we do not have an IRQ line */
|
|
+ if (!pcf85263->irq)
|
|
+ pcf85263->rtc->uie_unsupported = 1;
|
|
+
|
|
+ dev_info(pcf85263->dev,
|
|
+ "PCF85263 RTC (irqpin=%s irq=%d)\n",
|
|
+ pcf85263_irqpin_names[pcf85263->irq_pin],
|
|
+ pcf85263->irq);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int pcf85263_remove(struct i2c_client *client)
|
|
+{
|
|
+ struct pcf85263 *pcf85263 = i2c_get_clientdata(client);
|
|
+
|
|
+ if (pcf85263_can_wakeup_machine(pcf85263))
|
|
+ device_init_wakeup(pcf85263->dev, false);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
+static int pcf85263_suspend(struct device *dev)
|
|
+{
|
|
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
|
+ int ret = 0;
|
|
+
|
|
+ if (device_may_wakeup(dev))
|
|
+ ret = enable_irq_wake(pcf85263->irq);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int pcf85263_resume(struct device *dev)
|
|
+{
|
|
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
|
+ int ret = 0;
|
|
+
|
|
+ if (device_may_wakeup(dev))
|
|
+ ret = disable_irq_wake(pcf85263->irq);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+#endif
|
|
+
|
|
+static const struct i2c_device_id pcf85263_id[] = {
|
|
+ { "pcf85263", 0 },
|
|
+ { }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(i2c, pcf85263_id);
|
|
+
|
|
+#ifdef CONFIG_OF
|
|
+static const struct of_device_id pcf85263_of_match[] = {
|
|
+ { .compatible = "nxp,pcf85263" },
|
|
+ {}
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, pcf85263_of_match);
|
|
+#endif
|
|
+
|
|
+static SIMPLE_DEV_PM_OPS(pcf85263_pm_ops, pcf85263_suspend, pcf85263_resume);
|
|
+
|
|
+static struct i2c_driver pcf85263_driver = {
|
|
+ .driver = {
|
|
+ .name = "rtc-pcf85263",
|
|
+ .of_match_table = of_match_ptr(pcf85263_of_match),
|
|
+ .pm = &pcf85263_pm_ops,
|
|
+ },
|
|
+ .probe = pcf85263_probe,
|
|
+ .remove = pcf85263_remove,
|
|
+ .id_table = pcf85263_id,
|
|
+};
|
|
+
|
|
+module_i2c_driver(pcf85263_driver);
|
|
+
|
|
+MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
|
|
+MODULE_DESCRIPTION("PCF85263 RTC Driver");
|
|
+MODULE_LICENSE("GPL");
|
|
+
|