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Qualcomm claims this improves the D-cache footprint. Origina commit message below: From: Ben Menchaca <ben.menchaca@qca.qualcomm.com> Date: Fri, 7 Jun 2013 10:57:28 -0500 Subject: [ag71xx] cluster/align structs for cache perf Cluster the frequently used, per-packet structures in ag71xx near to each other, and cacheline-align them. Some other re-ordering occurred to move "warmer" structures near the per-packet structures. Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com> Signed-off-by: Rosen Penev <rosenp@gmail.com> |
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