4d5db712e3
The STP pinmux was initially added in assumption LAN2 led is driven by it. It worked somehow because STP group and gphy0 led0 share the GPIO. Do it the right way by adding the gphy0 led0 the gphy function. According to the author, the SPI node is a copy & paste leftover. Which makes sense since nothing is connected to the SPI bus on this device. Signed-off-by: Mathias Kresin <dev@kresin.me>
238 lines
4.3 KiB
Text
238 lines
4.3 KiB
Text
/include/ "vr9.dtsi"
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/ {
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model = "VGV7510KW22 - o2 Box 6431";
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chosen {
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bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
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leds {
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boot = &power_green;
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failsafe = &power_red;
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running = &power_green;
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dsl = &dsl;
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internet = &internet_green;
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wifi = &wifi;
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};
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};
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memory@0 {
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reg = <0x0 0x4000000>;
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};
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fpi@10000000 {
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localbus@0 {
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nor-boot@0 {
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compatible = "lantiq,nor";
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bank-width = <2>;
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reg = <0 0x0 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boardconfig: partition@fe0000 {
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label = "board_config";
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reg = <0xfe0000 0x20000>;
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read-only;
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};
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};
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};
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};
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gpio: pinmux@E100B10 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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ip101a-rst {
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lantiq,pins = "io46";
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lantiq,output = <0>;
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lantiq,pull = <1>;
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};
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gphy-leds {
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lantiq,groups = "gphy0 led0", "gphy0 led1",
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"gphy1 led0", "gphy1 led1";
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lantiq,function = "gphy";
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lantiq,open-drain = <0>;
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lantiq,pull = <2>;
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lantiq,output = <1>;
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};
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mdio {
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lantiq,groups = "mdio";
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lantiq,function = "mdio";
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};
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pci-rst {
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lantiq,pins = "io21";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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lantiq,output = <1>;
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};
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};
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};
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ifxhcd@E101000 {
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status = "okay";
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gpios = <&gpio 47 0>;
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};
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pci@E105400 {
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status = "okay";
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lantiq,bus-clock = <33333333>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30
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>;
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gpio-reset = <&gpio 21 0>;
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req-mask = <0x1>; /* GNT1 */
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};
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pcie@d900000 {
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status = "disabled";
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};
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};
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gphy-xrx200 {
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compatible = "lantiq,phy-xrx200";
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firmware1 = "lantiq/vr9_phy22f_a1x.bin"; /*VR9 1.1*/
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firmware2 = "lantiq/vr9_phy22f_a2x.bin"; /*VR9 1.2*/
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phys = [ 00 01 ];
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};
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ralink_eep {
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compatible = "ralink,eeprom";
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ralink,eeprom = "RT3062.eeprom";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <100>;
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reset {
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label = "reset";
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gpios = <&gpio 6 1>;
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linux,code = <0x198>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 9 1>;
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linux,code = <0x211>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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dsl: dsl {
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label = "vgv7510kw22:green:dsl";
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gpios = <&gpio 2 1>;
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};
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internet_red {
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label = "vgv7510kw22:red:internet";
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gpios = <&gpio 10 1>;
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};
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info_red {
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label = "vgv7510kw22:red:info";
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gpios = <&gpio 12 1>;
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};
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power_green: power {
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label = "vgv7510kw22:green:power";
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gpios = <&gpio 14 1>;
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default-state = "keep";
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};
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info_green {
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label = "vgv7510kw22:green:info";
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gpios = <&gpio 15 1>;
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};
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internet_green: internet_green {
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label = "vgv7510kw22:green:internet";
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gpios = <&gpio 19 1>;
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};
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wifi: wifi {
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label = "vgv7510kw22:green:wlan";
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gpios = <&gpio 20 1>;
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};
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power_red: power2 {
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label = "vgv7510kw22:red:power";
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gpios = <&gpio 28 1>;
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};
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phone {
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label = "vgv7510kw22:green:telefon";
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gpios = <&gpio 29 1>;
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};
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};
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};
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ð0 {
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lan: interface@0 {
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compatible = "lantiq,xrx200-pdi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mtd-mac-address = <&boardconfig 0x16>;
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lantiq,switch;
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ethernet@2 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <2>;
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phy-mode = "mii";
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phy-handle = <&phy11>;
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};
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ethernet@3 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <3>;
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phy-mode = "mii";
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phy-handle = <&phy12>;
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};
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ethernet@4 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <4>;
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phy-mode = "mii";
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phy-handle = <&phy13>;
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};
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ethernet@5 {
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compatible = "lantiq,xrx200-pdi-port";
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reg = <5>;
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phy-mode = "mii";
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phy-handle = <&phy14>;
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};
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};
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy12: ethernet-phy@12 {
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reg = <0x12>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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phy14: ethernet-phy@14 {
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reg = <0x14>;
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compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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