52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
From 46b62174f655edf6a4befae7f9871c431146b1b6 Mon Sep 17 00:00:00 2001
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From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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Date: Wed, 11 Sep 2013 14:17:47 -0500
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Subject: [PATCH 202/215] MIPS: Fix SMP core calculations when using MT
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support.
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The TCBIND register is only available if the core has MT support. It
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should not be read otherwise. Secondly, the number of TCs (siblings)
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are calculated differently depending on if the kernel is configured
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as SMVP or SMTC.
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Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
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Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/5822/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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(cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
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---
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arch/mips/kernel/smp-cmp.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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--- a/arch/mips/kernel/smp-cmp.c
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+++ b/arch/mips/kernel/smp-cmp.c
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@@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
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c->core = (read_c0_ebase() >> 1) & 0x1ff;
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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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- c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
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+ if (cpu_has_mipsmt)
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+ c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
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+ TCBIND_CURVPE;
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
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@@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
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}
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if (cpu_has_mipsmt) {
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- unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
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+ unsigned int nvpe = 1;
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+#ifdef CONFIG_MIPS_MT_SMP
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+ unsigned int mvpconf0 = read_c0_mvpconf0();
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+
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+ nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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+#elif defined(CONFIG_MIPS_MT_SMTC)
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+ unsigned int mvpconf0 = read_c0_mvpconf0();
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nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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+#endif
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smp_num_siblings = nvpe;
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}
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pr_info("Detected %i available secondary CPU(s)\n", ncpu);
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