d11efa1428
BCM6358 requires further work due to its shared TLB. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 36526
80 lines
2.6 KiB
Diff
80 lines
2.6 KiB
Diff
From 7c9d3fe01034adbb890aab7c44534658f89c211b Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 15:35:12 +0200
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Subject: [PATCH 08/13] MIPS: BCM63XX: use a helper for getting the right
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register address
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 30 ++++++++++++++++++++++++------
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1 file changed, 24 insertions(+), 6 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -251,6 +251,20 @@ static inline u32 get_ext_irq_perf_reg(i
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return ext_irq_cfg_reg2;
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}
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+static inline u32 get_irq_stat_addr(int cpu)
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+{
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+ if (cpu == 0)
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+ return irq_stat_addr0;
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+ return irq_stat_addr1;
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+}
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+
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+static inline u32 get_irq_mask_addr(int cpu)
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+{
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+ if (cpu == 0)
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+ return irq_mask_addr0;
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+ return irq_mask_addr1;
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+}
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+
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static inline void handle_internal(int intbit)
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{
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if (is_ext_irq_cascaded &&
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@@ -274,13 +288,15 @@ void __dispatch_internal_##width(void)
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unsigned int src, tgt; \
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bool irqs_pending = false; \
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static int i; \
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+ u32 irq_stat_addr = get_irq_stat_addr(0); \
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+ u32 irq_mask_addr = get_irq_mask_addr(0); \
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\
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/* read registers in reverse order */ \
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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\
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- val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \
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- val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \
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+ val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
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+ val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
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pending[--tgt] = val; \
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\
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if (val) \
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@@ -306,10 +322,11 @@ static void __internal_irq_mask_##width(
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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+ u32 irq_mask_addr = get_irq_mask_addr(0); \
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\
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- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
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+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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val &= ~(1 << bit); \
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- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
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+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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} \
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\
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static void __internal_irq_unmask_##width(unsigned int irq) \
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@@ -317,10 +334,11 @@ static void __internal_irq_unmask_##widt
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u32 val; \
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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+ u32 irq_mask_addr = get_irq_mask_addr(0); \
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\
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- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \
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+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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val |= (1 << bit); \
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- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \
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+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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}
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BUILD_IPIC_INTERNAL(32);
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