97 lines
3.5 KiB
Diff
97 lines
3.5 KiB
Diff
From 5db3b7ccb319679ac9c5791112c7eb42c25331e3 Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 23 May 2013 16:32:51 +0200
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Subject: [PATCH 17/29] pci: mvebu: no longer fake the slot location of
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downstream devices
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By default, the Marvell hardware, for each PCIe interface, exhibits
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the following devices:
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* On slot 0, a "Marvell Memory controller", identical on all PCIe
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interfaces, and which isn't useful when the Marvell SoC is the PCIe
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root complex (i.e, the normal case when we run Linux on the Marvell
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SoC).
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* On slot 1, the real PCIe card connected into the PCIe slot of the
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board.
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So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
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emulation is that when the Linux PCI core was trying to access the
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device in slot 0, we were in fact forwarding the configuration
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transaction to the device in slot 1. For all other slots, we were
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telling the Linux PCI core that there was no device connected.
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However, new versions of bootloaders from Marvell change the default
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PCIe configuration, and make the real device appear in slot 0, and the
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"Marvell Memory controller" in slot 1.
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Therefore, this commit modifies the Marvell PCIe driver to adjust the
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PCIe hardware configuration to make sure that this behavior (real
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device in slot 0, "Marvell Memory controller" in slot 1) is the one
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we'll see regardless of what the bootloader has done. It allows to
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remove the little hack that was forwarding configuration transactions
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on slot 0 to slot 1, which is nice.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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drivers/pci/host/pci-mvebu.c | 19 +++++++++++++++----
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1 file changed, 15 insertions(+), 4 deletions(-)
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -51,6 +51,7 @@
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_BUS 0xff00
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+#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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@@ -148,6 +149,16 @@ static void mvebu_pcie_set_local_bus_nr(
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writel(stat, port->base + PCIE_STAT_OFF);
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}
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+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
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+{
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+ u32 stat;
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+
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+ stat = readl(port->base + PCIE_STAT_OFF);
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+ stat &= ~PCIE_STAT_DEV;
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+ stat |= nr << 16;
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+ writel(stat, port->base + PCIE_STAT_OFF);
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+}
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+
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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@@ -572,8 +583,7 @@ static int mvebu_pcie_wr_conf(struct pci
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/* Access the real PCIe interface */
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spin_lock_irqsave(&port->conf_lock, flags);
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- ret = mvebu_pcie_hw_wr_conf(port, bus,
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- PCI_DEVFN(1, PCI_FUNC(devfn)),
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+ ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
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where, size, val);
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spin_unlock_irqrestore(&port->conf_lock, flags);
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@@ -606,8 +616,7 @@ static int mvebu_pcie_rd_conf(struct pci
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/* Access the real PCIe interface */
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spin_lock_irqsave(&port->conf_lock, flags);
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- ret = mvebu_pcie_hw_rd_conf(port, bus,
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- PCI_DEVFN(1, PCI_FUNC(devfn)),
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+ ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
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where, size, val);
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spin_unlock_irqrestore(&port->conf_lock, flags);
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@@ -817,6 +826,8 @@ static int __init mvebu_pcie_probe(struc
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continue;
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}
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+ mvebu_pcie_set_local_dev_nr(port, 1);
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+
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if (mvebu_pcie_link_up(port)) {
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port->haslink = 1;
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dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
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